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[v6,0/7] Add PCIe Root Port support for Agilex family of chips

Message ID 20250211151725.4133582-1-matthew.gerlach@linux.intel.com (mailing list archive)
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Series Add PCIe Root Port support for Agilex family of chips | expand

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Matthew Gerlach Feb. 11, 2025, 3:17 p.m. UTC 
This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.
Version 6 refactors duplicate dts snippets into dtsi's for correctness and
maintainability.

Patch 1:
  Add new compatible strings for the three variants of the Agilex PCIe controller IP.

Patch 2:
  Fix fixed-clock schema warnings in socfpga_agilex.dtsi before adding to it.

Patch 3:
  Move bus@80000000 dt node to socfpga_agilex.dtsi.

Patch 4:
  Refactor duplicate dts into dtsi.

Patch 5:
  Add base dtsi for PCIe Root Port support of the Agilex family of chips.

Patch 6:
  Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit.

Patch 7:
  Update Altera PCIe controller driver to support the Agilex family of chips.

D M, Sharath Kumar (1):
  PCI: altera: Add Agilex support

Matthew Gerlach (6):
  dt-bindings: PCI: altera: Add binding for Agilex
  arm64: dts: agilex: Fix fixed-clock schema warnings
  arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi
  arm64: dts: agilex: refactor shared dts into dtsi
  arm64: dts: agilex: add dtsi for PCIe Root Port
  arm64: dts: agilex: add dts enabling PCIe Root Port

 .../bindings/pci/altr,pcie-root-port.yaml     |  10 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  14 +
 .../socfpga_agilex7f_socdk_pcie_root_port.dts |  87 ++++++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   |  28 +-
 .../intel/socfpga_agilex_pcie_root_port.dtsi  |  48 ++++
 .../boot/dts/intel/socfpga_agilex_socdk.dts   |  62 +----
 .../boot/dts/intel/socfpga_agilex_socdk.dtsi  |  65 +++++
 .../dts/intel/socfpga_agilex_socdk_nand.dts   |  62 +----
 drivers/pci/controller/pcie-altera.c          | 253 +++++++++++++++++-
 10 files changed, 481 insertions(+), 149 deletions(-)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi