[v1,0/2] : PCI: PM: Improvements related to D3cold -> D0 transitions

Message ID	4198163.ejJDZkT8p0@kreacher (mailing list archive)
Headers	show Return-Path: <linux-pci-owner@kernel.org> From: "Rafael J. Wysocki" <rjw@rjwysocki.net> To: Linux PCI <linux-pci@vger.kernel.org> Cc: Linux PM <linux-pm@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>, Bjorn Helgaas <helgaas@kernel.org>, Mika Westerberg <mika.westerberg@linux.intel.com> Subject: [PATCH v1 0/2]: PCI: PM: Improvements related to D3cold -> D0 transitions Date: Mon, 04 Apr 2022 17:38:58 +0200 Message-ID: <4198163.ejJDZkT8p0@kreacher> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="UTF-8" Precedence: bulk
Series	: PCI: PM: Improvements related to D3cold -> D0 transitions \| expand [v1,0/2] : PCI: PM: Improvements related to D3cold -> D0 transitions [v1,1/2] PCI: PM: Avoid leaving devices in D0-uninitialized in pci_power_up() [v1,2/2] PCI: PM: Resume bus after putting the bridge into D0 entirely

Message ID

4198163.ejJDZkT8p0@kreacher (mailing list archive)

Headers

From: "Rafael J. Wysocki" <rjw@rjwysocki.net>
To: Linux PCI <linux-pci@vger.kernel.org>
Cc: Linux PM <linux-pm@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Bjorn Helgaas <helgaas@kernel.org>,
        Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH v1 0/2]: PCI: PM: Improvements related to D3cold -> D0
 transitions
Date: Mon, 04 Apr 2022 17:38:58 +0200
Message-ID: <4198163.ejJDZkT8p0@kreacher>
MIME-Version: 1.0
Content-Transfer-Encoding: 7Bit
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Series

: PCI: PM: Improvements related to D3cold -> D0 transitions | expand

Message

Rafael J. Wysocki April 4, 2022, 3:38 p.m. UTC

Hi All,

This series of two patches addresses potential issues related to transitions
of PCI devices from D3cold to D0.

The first one is that devices initially in D3cold may be left in D0-uninitialized
by pci_power_up() in some cases and the second one is that attempting to resume
PCI devices under a bridge that fails to go from D3cold to D0 is pointless.

Please refer to the patch changelogs for details.

Thanks!