diff mbox

Fix spelling of surprise

Message ID 1250807746.7142.2.camel@localhost.localdomain (mailing list archive)
State Accepted, archived
Headers show

Commit Message

Ed Swierk Aug. 20, 2009, 10:35 p.m. UTC 
It's surprise, not surpise or suprise.

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>

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Comments

Martin Mareš Aug. 21, 2009, 9:55 a.m. UTC | #1 
Hello!

> It's surprise, not surpise or suprise.

Thanks, applied.

				Have a nice fortnight
diff mbox

Patch

diff --git a/ls-caps.c b/ls-caps.c
index 634dadc..507771a 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -798,7 +798,7 @@  static void cap_express_slot(struct device *d, int where)
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
-  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 	FLAG(t, PCI_EXP_SLTCAP_ATNB),
 	FLAG(t, PCI_EXP_SLTCAP_PWRC),
 	FLAG(t, PCI_EXP_SLTCAP_MRL),
diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1
index f82b71d..b69184f 100644
--- a/tests/cap-pcie-1
+++ b/tests/cap-pcie-1
@@ -21,11 +21,11 @@ 
 			MaxPayload 256 bytes, MaxReadReq 128 bytes
 		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
 		LnkCap:	Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us
-			ClockPM- Suprise+ LLActRep+ BwNot+
+			ClockPM- Surprise+ LLActRep+ BwNot+
 		LnkCtl:	ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
 			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
 		LnkSta:	Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
-		SltCap:	AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surpise-
+		SltCap:	AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surprise-
 			Slot # 40, PowerLimit 0.000000; Interlock+ NoCompl-
 		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
 			Control: AttnInd Off, PwrInd Off, Power+ Interlock-
diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
index b7944a3..47c8953 100644
--- a/tests/cap-pcie-2
+++ b/tests/cap-pcie-2
@@ -26,7 +26,7 @@ 
 			MaxPayload 256 bytes, MaxReadReq 512 bytes
 		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
 		LnkCap:	Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us
-			ClockPM- Suprise- LLActRep- BwNot-
+			ClockPM- Surprise- LLActRep- BwNot-
 		LnkCtl:	ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
 			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
 		LnkSta:	Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-