| Message ID | 1365541601-14095-13-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Tue, Apr 09, 2013 at 11:06:33PM +0200, Thomas Petazzoni wrote: > The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the > necessary Device Tree informations to make these interfaces availabel. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > arch/arm/boot/dts/armada-370.dtsi | 51 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) Patches 12 through 18 applied to mvebu/dt. Now Gregory can rebase LPAE :) thx, Jason. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Apr 11, 2013 at 08:28:11PM -0400, Jason Cooper wrote: > On Tue, Apr 09, 2013 at 11:06:33PM +0200, Thomas Petazzoni wrote: > > The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the > > necessary Device Tree informations to make these interfaces availabel. > > > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > > --- > > arch/arm/boot/dts/armada-370.dtsi | 51 +++++++++++++++++++++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > Patches 12 through 18 applied to mvebu/dt. Now Gregory can rebase LPAE > :) Gregory, Hold off for an hour or so. I just realized that mvebu/fixes contains a few more relevant dts changes than I had pulled in to mvebu/dt. I'll let you know once I push an updated branch. thx, Jason. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 8188d13..2d9f8d6 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -153,5 +153,56 @@ clocks = <&coreclk 0>; }; + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>; + + reg-names = "pcie0.0", "pcie1.0"; + + ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ + 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ + 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 62>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; }; };
The Armada 370 SoC has two 1x PCIe 2.0 interfaces, so we add the necessary Device Tree informations to make these interfaces availabel. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- arch/arm/boot/dts/armada-370.dtsi | 51 +++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)