@@ -100,6 +100,9 @@ void pci_bus_remove_resources(struct pci_bus *bus)
/* The region that can be mapped by a 32-bit BAR. */
static struct pci_bus_region pci_32_bit = {0, 0xffffffff};
+/* The region that can be mapped by a 64-bit BAR above 4G */
+static struct pci_bus_region pci_64_bit = {(resource_size_t)(1ULL<<32),
+ (resource_size_t)(-1ULL)};
/*
* @res contains CPU addresses. Clip it so the corresponding bus addresses
@@ -150,12 +153,12 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
{
int i, ret = -ENOMEM;
struct resource *r;
- resource_size_t max;
type_mask |= IORESOURCE_IO | IORESOURCE_MEM;
pci_bus_for_each_resource(bus, r, i) {
struct resource avail;
+ int try_again = 0;
if (!r)
continue;
@@ -174,12 +177,19 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
* Unless this is a 64-bit BAR, we have to clip the
* available space to the part that maps to the region of
* 32-bit bus addresses.
+ * If this is a 64-bit BAR, try above 4G first.
*/
avail = *r;
if (!(res->flags & IORESOURCE_MEM_64)) {
pci_clip_resource_to_bus(bus, &avail, &pci_32_bit);
if (!resource_size(&avail))
continue;
+ } else {
+ pci_clip_resource_to_bus(bus, &avail, &pci_64_bit);
+ if (!resource_size(&avail))
+ avail = *r;
+ else
+ try_again = 1;
}
/*
@@ -188,16 +198,18 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
* this is an already-configured bridge window, its start
* overrides "min".
*/
- if (avail.start)
- min = avail.start;
-
- max = avail.end;
-
+again:
/* Ok, try it out.. */
- ret = allocate_resource(r, res, size, min, max,
- align, alignf, alignf_data);
+ ret = allocate_resource(r, res, size, avail.start ? : min,
+ avail.end, align, alignf, alignf_data);
if (ret == 0)
break;
+
+ if (try_again) {
+ avail = *r;
+ try_again = 0;
+ goto again;
+ }
}
return ret;
}
On system with more pcie cards, we do not have enough range under 4G to allocate those pci devices. On 64bit system, we could try to allocate mem64 above 4G at first, and fall back to below 4g if it can not find any above 4g. x86 32bit without X86_PAE support will have bottom set to 0, because resource_size_t is 32bit. For 32bit kernel that resource_size_t is 64bit when pae is support. we are safe because iomem_resource is limited to 32bit according to x86_phys_bits. -v2: update bottom assigning to make it clear for non-pae support machine. -v3: Bjorn's change: use MAX_RESOURCE instead of -1 use start/end instead of bottom/max for all arch instead of just x86_64 -v4: updated after PCI_MAX_RESOURCE_32 change. -v5: restore io handling to use PCI_MAX_RESOURCE_32 as limit. -v6: checking pcibios_resource_to_bus return for every bus res, to decide it if we need to try high at first. It supports all arches instead of just x86_64. -v7: split 4G limit change out to another patch according to Bjorn. also use pci_clip_resource instead. -v8: refresh after changes in pci/resource. Signed-off-by: Yinghai Lu <yinghai@kernel.org> --- drivers/pci/bus.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-)