| Message ID | 1441897138-23251-2-git-send-email-gabriele.paoloni@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
Hi Gab, On Thu, Sep 10, 2015 at 8:28 PM, Gabriele Paoloni <gabriele.paoloni@huawei.com> wrote: > From: gabriele paoloni <gabriele.paoloni@huawei.com> > > Currently spear13xx passes the wrong "address" in many calls to > dw_pcie_cfg_read and dw_pcie_cfg_write: the passed address is > always pp->dbi_base, that is wrong as it does not consider > the offset to access the right register of the PCI header. > This patches fixes these function calls passing the address to > access the right register. Thanks for the effort, however there were some more issues with current implementation. Like PCI_EXP_DEVCTL is only two bytes of register. Next two bytes are PCI_EXP_DEVSTS which is RO, so writing 4 bytes at offset 'exp_cap_off + PCI_EXP_DEVCTL' is not correct. I had sent a patch to correct all the issues with current implementation [1]. You can take that as your 1st patch. [1] https://lkml.org/lkml/2015/9/7/5 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Pratyush Anand [mailto:pratyush.anand@gmail.com] > Sent: Thursday, September 10, 2015 5:30 PM > To: Gabriele Paoloni; Bjorn Helgaas > Cc: Jingoo Han; linux-pci@vger.kernel.org; Wangzhou (B); Yuanzhichang; > Zhudacai; zhangjukuo; qiuzhenfa; Liguozhu (Kenneth) > Subject: Re: [PATCH v2 1/3] PCI: spear13xx: fix addresses in > dw_pcie_cfg_read and dw_pcie_cfg_write > > Hi Gab, > > On Thu, Sep 10, 2015 at 8:28 PM, Gabriele Paoloni > <gabriele.paoloni@huawei.com> wrote: > > From: gabriele paoloni <gabriele.paoloni@huawei.com> > > > > Currently spear13xx passes the wrong "address" in many calls to > > dw_pcie_cfg_read and dw_pcie_cfg_write: the passed address is > > always pp->dbi_base, that is wrong as it does not consider > > the offset to access the right register of the PCI header. > > This patches fixes these function calls passing the address to > > access the right register. > > Thanks for the effort, however there were some more issues with > current implementation. > Like PCI_EXP_DEVCTL is only two bytes of register. Next two bytes are > PCI_EXP_DEVSTS which is RO, so writing 4 bytes at offset 'exp_cap_off > + PCI_EXP_DEVCTL' is not correct. > > I had sent a patch to correct all the issues with current > implementation [1]. You can take that as your 1st patch. Oops Sorry, I missed that patch! I'll take it as patch 1, Many Thanks Gab > > [1] https://lkml.org/lkml/2015/9/7/5
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index c49fbdc..5f3513b 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -146,6 +146,7 @@ struct pcie_app_reg { static int spear13xx_pcie_establish_link(struct pcie_port *pp) { u32 val; + int where; struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; u32 exp_cap_off = EXP_CAP_ID_OFFSET; @@ -163,9 +164,10 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) * default value in capability register is 512 bytes. So force * it to 128 here. */ - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val); + where = exp_cap_off + PCI_EXP_DEVCTL; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); val &= ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, 4, val); dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A); dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80); @@ -175,22 +177,24 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) * also works */ if (spear13xx_pcie->is_gen1) { - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4, + where = exp_cap_off + PCI_EXP_LNKCAP; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + - PCI_EXP_LNKCAP, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), + where, 4, val); } - dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4, + where = exp_cap_off + PCI_EXP_LNKCTL2; + dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + - PCI_EXP_LNKCTL2, 4, val); + dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), + where, 4, val); } }