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[v4,1/3] PCIE: spear13xx: fix addresses in dw_pcie_cfg_read and dw_pcie_cfg_write

Message ID 1443526447-228817-2-git-send-email-gabriele.paoloni@huawei.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Gabriele Paoloni Sept. 29, 2015, 11:34 a.m. UTC 
From: gabriele paoloni <gabriele.paoloni@huawei.com>

Currently spear13xx passes the wrong "address" in many calls to
dw_pcie_cfg_read and dw_pcie_cfg_write: the passed address is
always pp->dbi_base, that is wrong as it does not consider
the offset to access the right register of the PCI header.
This patches fixes these function calls passing the address to
access the right register.

Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
 drivers/pci/host/pcie-spear13xx.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)
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Patch

diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index 98d2683..a5997e3 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -146,6 +146,7 @@  struct pcie_app_reg {
 static int spear13xx_pcie_establish_link(struct pcie_port *pp)
 {
 	u32 val;
+	int where;
 	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
 	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
@@ -163,9 +164,10 @@  static int spear13xx_pcie_establish_link(struct pcie_port *pp)
 	 * default value in capability register is 512 bytes. So force
 	 * it to 128 here.
 	 */
-	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+	where = exp_cap_off + PCI_EXP_DEVCTL;
+	dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4, &val);
 	val &= ~PCI_EXP_DEVCTL_READRQ;
-	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+	dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, 4, val);
 
 	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
 	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
@@ -175,22 +177,24 @@  static int spear13xx_pcie_establish_link(struct pcie_port *pp)
 	 * also works
 	 */
 	if (spear13xx_pcie->is_gen1) {
-		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+		where = exp_cap_off + PCI_EXP_LNKCAP;
+		dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4,
 				 &val);
 		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
-					  PCI_EXP_LNKCAP, 4, val);
+			dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+					where, 4, val);
 		}
 
-		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+		where = exp_cap_off + PCI_EXP_LNKCTL2;
+		dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, 4,
 				 &val);
 		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
 			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
-			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
-					  PCI_EXP_LNKCTL2, 4, val);
+			dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+					where, 4, val);
 		}
 	}