diff mbox

[1/2] PCI: spear: Move LTSSM state definitions to pcie-designware.h

Message ID 1443906691-14642-1-git-send-email-festevam@gmail.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Fabio Estevam Oct. 3, 2015, 9:11 p.m. UTC 
From: Fabio Estevam <fabio.estevam@freescale.com>

Move LTSSM state definitions to common pcie-designware.h so that other
drivers can make use of them.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++
 drivers/pci/host/pcie-spear13xx.c  | 33 ---------------------------------
 2 files changed, 34 insertions(+), 33 deletions(-)

Comments

Pratyush Anand Oct. 4, 2015, 11:40 a.m. UTC | #1 
On Sun, Oct 4, 2015 at 2:41 AM, Fabio Estevam <festevam@gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Move LTSSM state definitions to common pcie-designware.h so that other
> drivers can make use of them.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Yes, they are designware specific. So can be moved.

Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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kernel test robot Oct. 4, 2015, 1:41 p.m. UTC | #2 
Hi Fabio,

[auto build test results on next-20151002 -- if it's inappropriate base, please ignore]

config: arm-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

>> drivers/pci/host/pci-keystone-dw.c:28:0: warning: "LTSSM_STATE_MASK" redefined
    #define LTSSM_STATE_MASK  0x1f
    ^
   In file included from drivers/pci/host/pci-keystone-dw.c:23:0:
   drivers/pci/host/pcie-designware.h:57:0: note: this is the location of the previous definition
    #define LTSSM_STATE_MASK  0x3F
    ^
--
>> drivers/pci/host/pci-layerscape.c:32:0: warning: "LTSSM_STATE_MASK" redefined
    #define LTSSM_STATE_MASK 0x3f
    ^
   In file included from drivers/pci/host/pci-layerscape.c:27:0:
   drivers/pci/host/pcie-designware.h:57:0: note: this is the location of the previous definition
    #define LTSSM_STATE_MASK  0x3F
    ^

vim +/LTSSM_STATE_MASK +28 drivers/pci/host/pci-keystone-dw.c

0c4ffcfe Murali Karicheri 2014-09-02  12   * published by the Free Software Foundation.
0c4ffcfe Murali Karicheri 2014-09-02  13   */
0c4ffcfe Murali Karicheri 2014-09-02  14  
0c4ffcfe Murali Karicheri 2014-09-02  15  #include <linux/irq.h>
0c4ffcfe Murali Karicheri 2014-09-02  16  #include <linux/irqdomain.h>
0c4ffcfe Murali Karicheri 2014-09-02  17  #include <linux/module.h>
0c4ffcfe Murali Karicheri 2014-09-02  18  #include <linux/of.h>
0c4ffcfe Murali Karicheri 2014-09-02  19  #include <linux/of_pci.h>
0c4ffcfe Murali Karicheri 2014-09-02  20  #include <linux/pci.h>
0c4ffcfe Murali Karicheri 2014-09-02  21  #include <linux/platform_device.h>
0c4ffcfe Murali Karicheri 2014-09-02  22  
0c4ffcfe Murali Karicheri 2014-09-02  23  #include "pcie-designware.h"
0c4ffcfe Murali Karicheri 2014-09-02  24  #include "pci-keystone.h"
0c4ffcfe Murali Karicheri 2014-09-02  25  
0c4ffcfe Murali Karicheri 2014-09-02  26  /* Application register defines */
0c4ffcfe Murali Karicheri 2014-09-02  27  #define LTSSM_EN_VAL		        1
0c4ffcfe Murali Karicheri 2014-09-02 @28  #define LTSSM_STATE_MASK		0x1f
0c4ffcfe Murali Karicheri 2014-09-02  29  #define LTSSM_STATE_L0			0x11
0c4ffcfe Murali Karicheri 2014-09-02  30  #define DBI_CS2_EN_VAL			0x20
0c4ffcfe Murali Karicheri 2014-09-02  31  #define OB_XLAT_EN_VAL		        2
0c4ffcfe Murali Karicheri 2014-09-02  32  
0c4ffcfe Murali Karicheri 2014-09-02  33  /* Application registers */
0c4ffcfe Murali Karicheri 2014-09-02  34  #define CMD_STATUS			0x004
0c4ffcfe Murali Karicheri 2014-09-02  35  #define CFG_SETUP			0x008
0c4ffcfe Murali Karicheri 2014-09-02  36  #define OB_SIZE				0x030

:::::: The code at line 28 was first introduced by commit
:::::: 0c4ffcfe1fbc1ef564ec137eab21137cb013b00e PCI: keystone: Add TI Keystone PCIe driver

:::::: TO: Murali Karicheri <m-karicheri2@ti.com>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 35123d9..97d6558 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,6 +22,40 @@ 
 #define MAX_MSI_IRQS			32
 #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
 
+#define LTSSM_STATE_DETECT_QUIET	0x00
+#define LTSSM_STATE_DETECT_ACT		0x01
+#define LTSSM_STATE_POLL_ACTIVE		0x02
+#define LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define LTSSM_STATE_POLL_CONFIG		0x04
+#define LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define LTSSM_STATE_DETECT_WAIT		0x06
+#define LTSSM_STATE_CFG_LINKWD_START	0x07
+#define LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
+#define LTSSM_STATE_CFG_COMPLETE	0x0B
+#define LTSSM_STATE_CFG_IDLE		0x0C
+#define LTSSM_STATE_RCVRY_LOCK		0x0D
+#define LTSSM_STATE_RCVRY_SPEED		0x0E
+#define LTSSM_STATE_RCVRY_RCVRCFG	0x0F
+#define LTSSM_STATE_RCVRY_IDLE		0x10
+#define LTSSM_STATE_L0			0x11
+#define LTSSM_STATE_L0S			0x12
+#define LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define LTSSM_STATE_L1_IDLE		0x14
+#define LTSSM_STATE_L2_IDLE		0x15
+#define LTSSM_STATE_L2_WAKE		0x16
+#define LTSSM_STATE_DISABLED_ENTRY	0x17
+#define LTSSM_STATE_DISABLED_IDLE	0x18
+#define LTSSM_STATE_DISABLED		0x19
+#define LTSSM_STATE_LPBK_ENTRY		0x1A
+#define LTSSM_STATE_LPBK_ACTIVE		0x1B
+#define LTSSM_STATE_LPBK_EXIT		0x1C
+#define LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
+#define LTSSM_STATE_HOT_RESET_ENTRY	0x1E
+#define LTSSM_STATE_HOT_RESET		0x1F
+#define LTSSM_STATE_MASK		0x3F
+
 struct pcie_port {
 	struct device		*dev;
 	u8			root_bus_nr;
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index 98d2683..920d399 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -84,39 +84,6 @@  struct pcie_app_reg {
 #define APPS_PM_XMT_PME_ID			5
 
 /* CR3 ID */
-#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
-#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
-#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
-#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
-#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
-#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
-#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
-#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
-#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
-#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
-#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
-#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
-#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
-#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
-#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
-#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
-#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
-#define XMLH_LTSSM_STATE_L0			0x11
-#define XMLH_LTSSM_STATE_L0S			0x12
-#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
-#define XMLH_LTSSM_STATE_L1_IDLE		0x14
-#define XMLH_LTSSM_STATE_L2_IDLE		0x15
-#define XMLH_LTSSM_STATE_L2_WAKE		0x16
-#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
-#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
-#define XMLH_LTSSM_STATE_DISABLED		0x19
-#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
-#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
-#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
-#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
-#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
-#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
-#define XMLH_LTSSM_STATE_MASK			0x3F
 #define XMLH_LINK_UP				(1 << 6)
 
 /* CR4 ID */