diff mbox

PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders

Message ID 1503187634-3823-1-git-send-email-festevam@gmail.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Fabio Estevam Aug. 20, 2017, 12:07 a.m. UTC
The reset GPIO can be connected to a I2C or SPI IO expander, which may
sleep, so it is safer to use the gpiod_set_value_cansleep() variant
instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 drivers/pci/host/pcie-rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Bjorn Helgaas Aug. 24, 2017, 4:33 p.m. UTC | #1
On Sat, Aug 19, 2017 at 09:07:14PM -0300, Fabio Estevam wrote:
> The reset GPIO can be connected to a I2C or SPI IO expander, which may
> sleep, so it is safer to use the gpiod_set_value_cansleep() variant
> instead.
> 
> Signed-off-by: Fabio Estevam <festevam@gmail.com>

Waiting for Shawn's ack...

> ---
>  drivers/pci/host/pcie-rockchip.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 2eccd53..124b280 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -537,7 +537,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  	int err, i;
>  	u32 status;
>  
> -	gpiod_set_value(rockchip->ep_gpio, 0);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
>  
>  	err = reset_control_assert(rockchip->aclk_rst);
>  	if (err) {
> @@ -682,7 +682,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
>  			    PCIE_CLIENT_CONFIG);
>  
> -	gpiod_set_value(rockchip->ep_gpio, 1);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
>  
>  	/* 500ms timeout value should be enough for Gen1/2 training */
>  	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> -- 
> 2.7.4
>
Heiko Stübner Aug. 24, 2017, 4:37 p.m. UTC | #2
Am Donnerstag, 24. August 2017, 11:33:23 CEST schrieb Bjorn Helgaas:
> On Sat, Aug 19, 2017 at 09:07:14PM -0300, Fabio Estevam wrote:
> > The reset GPIO can be connected to a I2C or SPI IO expander, which may
> > sleep, so it is safer to use the gpiod_set_value_cansleep() variant
> > instead.
> > 
> > Signed-off-by: Fabio Estevam <festevam@gmail.com>
> 
> Waiting for Shawn's ack...

we might want to include him then, as I'm not sure if he patrols the
linux-pci list :-) . [I've added him]


> 
> > ---
> >  drivers/pci/host/pcie-rockchip.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> > index 2eccd53..124b280 100644
> > --- a/drivers/pci/host/pcie-rockchip.c
> > +++ b/drivers/pci/host/pcie-rockchip.c
> > @@ -537,7 +537,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> >  	int err, i;
> >  	u32 status;
> >  
> > -	gpiod_set_value(rockchip->ep_gpio, 0);
> > +	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
> >  
> >  	err = reset_control_assert(rockchip->aclk_rst);
> >  	if (err) {
> > @@ -682,7 +682,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
> >  	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> >  			    PCIE_CLIENT_CONFIG);
> >  
> > -	gpiod_set_value(rockchip->ep_gpio, 1);
> > +	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
> >  
> >  	/* 500ms timeout value should be enough for Gen1/2 training */
> >  	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> 
>
Fabio Estevam Aug. 28, 2017, 12:27 a.m. UTC | #3
On Thu, Aug 24, 2017 at 1:37 PM, Heiko Stuebner <heiko@sntech.de> wrote:

>> Waiting for Shawn's ack...
>
> we might want to include him then, as I'm not sure if he patrols the
> linux-pci list :-) . [I've added him]

Sorry, I missed to add Shawn on Cc. I have just resent the patch with him on Cc.

Thanks
Shawn Lin Aug. 28, 2017, 12:46 a.m. UTC | #4
On 2017/8/28 8:27, Fabio Estevam wrote:
> On Thu, Aug 24, 2017 at 1:37 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> 
>>> Waiting for Shawn's ack...
>>
>> we might want to include him then, as I'm not sure if he patrols the
>> linux-pci list :-) . [I've added him]

Aha, I also patrol linux-rockchip for pcie-rockchip, but this patch
didn't include it either.

> 
> Sorry, I missed to add Shawn on Cc. I have just resent the patch with him on Cc.
> 

Don't worry. I will check it out ASAP.

> Thanks
> 
> 
>
diff mbox

Patch

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 2eccd53..124b280 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -537,7 +537,7 @@  static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	int err, i;
 	u32 status;
 
-	gpiod_set_value(rockchip->ep_gpio, 0);
+	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
 
 	err = reset_control_assert(rockchip->aclk_rst);
 	if (err) {
@@ -682,7 +682,7 @@  static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
 			    PCIE_CLIENT_CONFIG);
 
-	gpiod_set_value(rockchip->ep_gpio, 1);
+	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,