diff mbox

[RESEND] PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders

Message ID 1503879957-30008-1-git-send-email-festevam@gmail.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Fabio Estevam Aug. 28, 2017, 12:25 a.m. UTC
The reset GPIO can be connected to a I2C or SPI IO expander, which may
sleep, so it is safer to use the gpiod_set_value_cansleep() variant
instead.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Changes since v1:
- Resending with Shawn Lin added on Cc.

 drivers/pci/host/pcie-rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Shawn Lin Aug. 28, 2017, 1:17 a.m. UTC | #1
On 2017/8/28 8:25, Fabio Estevam wrote:
> The reset GPIO can be connected to a I2C or SPI IO expander, which may
> sleep, so it is safer to use the gpiod_set_value_cansleep() variant
> instead.
> 
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
> Changes since v1:
> - Resending with Shawn Lin added on Cc.
> 
>   drivers/pci/host/pcie-rockchip.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Shawn Lin <shawn.lin@rock-chips.com>

> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 2eccd53..124b280 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -537,7 +537,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>   	int err, i;
>   	u32 status;
>   
> -	gpiod_set_value(rockchip->ep_gpio, 0);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
>   
>   	err = reset_control_assert(rockchip->aclk_rst);
>   	if (err) {
> @@ -682,7 +682,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>   	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
>   			    PCIE_CLIENT_CONFIG);
>   
> -	gpiod_set_value(rockchip->ep_gpio, 1);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
>   
>   	/* 500ms timeout value should be enough for Gen1/2 training */
>   	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
>
Bjorn Helgaas Aug. 28, 2017, 6:17 p.m. UTC | #2
On Sun, Aug 27, 2017 at 09:25:57PM -0300, Fabio Estevam wrote:
> The reset GPIO can be connected to a I2C or SPI IO expander, which may
> sleep, so it is safer to use the gpiod_set_value_cansleep() variant
> instead.
> 
> Signed-off-by: Fabio Estevam <festevam@gmail.com>

Applied with Shawn's ack to pci/host-rockchip for v4.14, thanks!

> ---
> Changes since v1:
> - Resending with Shawn Lin added on Cc.
> 
>  drivers/pci/host/pcie-rockchip.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 2eccd53..124b280 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -537,7 +537,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  	int err, i;
>  	u32 status;
>  
> -	gpiod_set_value(rockchip->ep_gpio, 0);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
>  
>  	err = reset_control_assert(rockchip->aclk_rst);
>  	if (err) {
> @@ -682,7 +682,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>  	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
>  			    PCIE_CLIENT_CONFIG);
>  
> -	gpiod_set_value(rockchip->ep_gpio, 1);
> +	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
>  
>  	/* 500ms timeout value should be enough for Gen1/2 training */
>  	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> -- 
> 2.7.4
>
diff mbox

Patch

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 2eccd53..124b280 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -537,7 +537,7 @@  static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	int err, i;
 	u32 status;
 
-	gpiod_set_value(rockchip->ep_gpio, 0);
+	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
 
 	err = reset_control_assert(rockchip->aclk_rst);
 	if (err) {
@@ -682,7 +682,7 @@  static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
 			    PCIE_CLIENT_CONFIG);
 
-	gpiod_set_value(rockchip->ep_gpio, 1);
+	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
 
 	/* 500ms timeout value should be enough for Gen1/2 training */
 	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,