| Message ID | 1608771161-34681-1-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: rockchip: Correct definition of ROCKCHIP_PCIE_EP_MSI_CTRL_ME | expand |
On Thu, Dec 24, 2020 at 08:52:41AM +0800, Shawn Lin wrote: > ROCKCHIP_PCIE_EP_MSI_CTRL_ME should be BIT(0), and fix the flags > to be u32 type. We need two patches, two logical changes. I will drop this patch waiting for those. Lorenzo > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > --- > > drivers/pci/controller/pcie-rockchip-ep.c | 7 ++++--- > drivers/pci/controller/pcie-rockchip.h | 2 +- > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index 7631dc3..a25e212 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -313,7 +313,7 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, > { > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > struct rockchip_pcie *rockchip = &ep->rockchip; > - u16 flags; > + u32 flags; > > flags = rockchip_pcie_read(rockchip, > ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > @@ -333,7 +333,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) > { > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > struct rockchip_pcie *rockchip = &ep->rockchip; > - u16 flags; > + u32 flags; > > flags = rockchip_pcie_read(rockchip, > ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > @@ -417,7 +417,8 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, > u8 interrupt_num) > { > struct rockchip_pcie *rockchip = &ep->rockchip; > - u16 flags, mme, data, data_mask; > + u16 mme, data, data_mask; > + u32 flags; > u8 msi_count; > u64 pci_addr, pci_addr_mask = 0xff; > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 1650a50..c668268 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -221,7 +221,7 @@ > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20) > -#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(0) > #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) > #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 > #define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 > -- > 2.7.4 > > >
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 7631dc3..a25e212 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -313,7 +313,7 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -333,7 +333,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -417,7 +417,8 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags, mme, data, data_mask; + u16 mme, data, data_mask; + u32 flags; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 1650a50..c668268 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -221,7 +221,7 @@ #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20) -#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) +#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(0) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 #define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3
ROCKCHIP_PCIE_EP_MSI_CTRL_ME should be BIT(0), and fix the flags to be u32 type. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/pci/controller/pcie-rockchip-ep.c | 7 ++++--- drivers/pci/controller/pcie-rockchip.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-)