| Message ID | 1616661882-26487-4-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | add one regulator used to power up pcie phy | expand |
Hi, > + /* > + * Regarding to the datasheet, the PCIE_VPH is suggested > + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the > + * VREG_BYPASS should be cleared to zero. > + */ [...] A small nitpick here. What about the following: Regarding the data sheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is supplied with 3.3V, the VREG_BYPASS should be cleared to zero. What do you think? Krzysztof
Am Donnerstag, dem 25.03.2021 um 16:44 +0800 schrieb Richard Zhu: > Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. > In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data > sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, > the VREG_BYPASS bits of GPR registers should be cleared from default > value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be > turned on. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 853ea8e82952..d9d534f0840f 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -37,6 +37,7 @@ > #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) > +#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) > #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 > > > > > @@ -80,6 +81,7 @@ struct imx6_pcie { > u32 tx_swing_full; > u32 tx_swing_low; > struct regulator *vpcie; > + struct regulator *vph; > void __iomem *phy_base; > > > > > /* power domain for pcie */ > @@ -621,6 +623,17 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) > imx6_pcie_grp_offset(imx6_pcie), > IMX8MQ_GPR_PCIE_REF_USE_PAD, > IMX8MQ_GPR_PCIE_REF_USE_PAD); > + /* > + * Regarding to the datasheet, the PCIE_VPH is suggested > + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the > + * VREG_BYPASS should be cleared to zero. > + */ > + if (imx6_pcie->vph && > + regulator_get_voltage(imx6_pcie->vph) > 3000000) > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > + imx6_pcie_grp_offset(imx6_pcie), > + IMX8MQ_GPR_PCIE_VREG_BYPASS, > + 0); > break; > case IMX7D: > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > @@ -1130,6 +1143,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) > imx6_pcie->vpcie = NULL; > } > > > > > + imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); > + if (IS_ERR(imx6_pcie->vph)) { > + if (PTR_ERR(imx6_pcie->vph) != -ENODEV) > + return PTR_ERR(imx6_pcie->vph); > + imx6_pcie->vph = NULL; > + } > + > platform_set_drvdata(pdev, imx6_pcie); > > > > > ret = imx6_pcie_attach_pd(dev);
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 853ea8e82952..d9d534f0840f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -37,6 +37,7 @@ #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) +#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 @@ -80,6 +81,7 @@ struct imx6_pcie { u32 tx_swing_full; u32 tx_swing_low; struct regulator *vpcie; + struct regulator *vph; void __iomem *phy_base; /* power domain for pcie */ @@ -621,6 +623,17 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) imx6_pcie_grp_offset(imx6_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, IMX8MQ_GPR_PCIE_REF_USE_PAD); + /* + * Regarding to the datasheet, the PCIE_VPH is suggested + * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the + * VREG_BYPASS should be cleared to zero. + */ + if (imx6_pcie->vph && + regulator_get_voltage(imx6_pcie->vph) > 3000000) + regmap_update_bits(imx6_pcie->iomuxc_gpr, + imx6_pcie_grp_offset(imx6_pcie), + IMX8MQ_GPR_PCIE_VREG_BYPASS, + 0); break; case IMX7D: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1130,6 +1143,13 @@ static int imx6_pcie_probe(struct platform_device *pdev) imx6_pcie->vpcie = NULL; } + imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); + if (IS_ERR(imx6_pcie->vph)) { + if (PTR_ERR(imx6_pcie->vph) != -ENODEV) + return PTR_ERR(imx6_pcie->vph); + imx6_pcie->vph = NULL; + } + platform_set_drvdata(pdev, imx6_pcie); ret = imx6_pcie_attach_pd(dev);
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)