| Message ID | 1661845564-11373-5-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add the iMX8MP PCIe support | expand |
Hi, On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote: > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) > of SRC_PCIEPHY_RCR is 1b'1. > But i.MX8MP has one inversed default value 1b'0 of PERST bit. > > And the PERST bit should be kept 1b'1 after power and clocks are stable. > So fix the i.MX8MP PCIe PHY PERST support here. > > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> > Tested-by: Richard Leitner <richard.leitner@skidata.com> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> I've applied this patch to the reset/fixes branch. regards Philipp
> -----Original Message----- > From: Philipp Zabel <p.zabel@pengutronix.de> > Sent: 2022年8月31日 0:46 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de; > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org; > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com; > marex@denx.de; richard.leitner@linux.dev > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST > support > > Hi, > > On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote: > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. > > But i.MX8MP has one inversed default value 1b'0 of PERST bit. > > > > And the PERST bit should be kept 1b'1 after power and clocks are stable. > > So fix the i.MX8MP PCIe PHY PERST support here. > > > > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > > Tested-by: Marek Vasut <marex@denx.de> > > Tested-by: Richard Leitner <richard.leitner@skidata.com> > > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> > > I've applied this patch to the reset/fixes branch. > Thanks a lot. Best Regards Richard Zhu > regards > Philipp
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 185a333df66c..d2408725eb2c 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev, break; case IMX8MP_RESET_PCIE_CTRL_APPS_EN: + case IMX8MP_RESET_PCIEPHY_PERST: value = assert ? 0 : bit; break; }
On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. But i.MX8MP has one inversed default value 1b'0 of PERST bit. And the PERST bit should be kept 1b'1 after power and clocks are stable. So fix the i.MX8MP PCIe PHY PERST support here. Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> --- drivers/reset/reset-imx7.c | 1 + 1 file changed, 1 insertion(+)