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[2/2] PCI: Support PCIe Capability Slot registers only for ports with slots

Message ID 20131118191752.26774.25303.stgit@bhelgaas-glaptop.roam.corp.google.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Bjorn Helgaas Nov. 18, 2013, 7:17 p.m. UTC 
Commit 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e upstream.

Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.

It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability.  However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
CC: stable@vger.kernel.org	# 3.10.x 3.11.x
---
 drivers/pci/access.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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diff mbox

Patch

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index e26c3bd9aca4..bcd92b629d3c 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -499,8 +499,8 @@  static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
 	int type = pci_pcie_type(dev);
 
 	return pcie_cap_version(dev) > 1 ||
-	       type == PCI_EXP_TYPE_ROOT_PORT ||
-	       (type == PCI_EXP_TYPE_DOWNSTREAM &&
+	       ((type == PCI_EXP_TYPE_ROOT_PORT ||
+	         type == PCI_EXP_TYPE_DOWNSTREAM) &&
 		pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);
 }