| Message ID | 20170515062745.70082-1-songxiaowei@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
Hello Song You forgot to add the device tree maintainers and the device tree mailing list to this patch. If you use ./scripts/get_maintainer.pl <patch> it will show you this information. Regards, Niklas On 05/15/2017 08:27 AM, Song Xiaowei wrote: > Add PCIe node for hi3660, and add binding documentation. > > Cc: Guodong Xu <guodong.xu@linaro.org> > Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com> > --- > .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++ > 2 files changed, 83 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > index a339dbb15493..71491178c86c 100644 > --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > @@ -85,3 +85,55 @@ Example: > 0x0 0 0 4 &mbigen_pcie0 650 4>; > status = "ok"; > }; > + > + > + > +HiSilicon Kirin SoC PCIe host DT description > + > +Kirin PCIe host controller is also based on Designware PCI core. > +It shares common functions with PCIe Designware core driver and inherits > +common properties defined in > +Documentation/devicetree/bindings/pci/designware-pci.txt. > + > +Additional properties are described here: > + > +Required properties > +- compatible: Should contain "hisilicon,kirin-pcie". > +- reg: Should contain rc_dbi, apb, phy, config registers location and length. > +- reg-names: Must include the following entries: > + "dbi": controller configuration registers; > + "apb": apb Ctrl register; > + "phy": apb PHY register; > + "config": PCIe configuration space registers. > +- reset-gpio: perst assert/deassert gpio > + > +Optional properties: > +- status: Either "ok" or "disabled". > + > +Kirin960 Example: > + kirin_pcie@f4000000 { > + compatible = "hisilicon,kirin-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>; > + reg-names = "dbi","apb","phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>, > + <0x0 0 0 3 &gic 0 0 0 284 4>, > + <0x0 0 0 4 &gic 0 0 0 285 4>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; > + reset-gpio = <&gpio11 1 0 >; > + status = "ok"; > + }; > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index 3983086bd67b..2406a54947df 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -156,5 +156,36 @@ > clock-names = "uartclk", "apb_pclk"; > status = "disabled"; > }; > + > + kirin_pcie@f4000000 { > + compatible = "hisilicon,kirin-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, > + <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, > + <0x0 0xF5000000 0x0 0x2000>; > + reg-names = "dbi", "apb", "phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 > + 0xf6000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, > + <0x0 0 0 2 &gic 0 0 0 283 4>, > + <0x0 0 0 3 &gic 0 0 0 284 4>, > + <0x0 0 0 4 &gic 0 0 0 285 4>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; > + reset-gpio = <&gpio11 1 0 >; > + status = "ok"; > + }; > }; > }; >
Hi Song,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc1 next-20170515]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
This PCIe node has dependencies on &crg_ctrl and &gpio11. However, both of them are not appearing in mainline kernel tree yet. Sorry about that. But I do have a plan to send all dts related changes to maillist within this week, no later than this Wed (17/May). Would it be possible you maintainers review this patch in parallel? +Device tree maintainers. -Guodong > > On Mon, May 15, 2017 at 5:18 PM, kbuild test robot <lkp@intel.com> wrote: >> >> Hi Song, >> >> [auto build test ERROR on pci/next] >> [also build test ERROR on v4.12-rc1 next-20170515] >> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] >> >> url: https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035 >> base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next >> config: arm64-defconfig (attached as .config) >> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 >> reproduce: >> wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross >> chmod +x ~/bin/make.cross >> # save the attached .config to linux build tree >> make.cross ARCH=arm64 >> >> All errors (new ones prefixed by >>): >> >> >> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error >> FATAL ERROR: Unable to parse input tree >> >> --- >> 0-DAY kernel test infrastructure Open Source Technology Center >> https://lists.01.org/pipermail/kbuild-all Intel Corporation > >
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index a339dbb15493..71491178c86c 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -85,3 +85,55 @@ Example: 0x0 0 0 4 &mbigen_pcie0 650 4>; status = "ok"; }; + + + +HiSilicon Kirin SoC PCIe host DT description + +Kirin PCIe host controller is also based on Designware PCI core. +It shares common functions with PCIe Designware core driver and inherits +common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties +- compatible: Should contain "hisilicon,kirin-pcie". +- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg-names: Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register; + "phy": apb PHY register; + "config": PCIe configuration space registers. +- reset-gpio: perst assert/deassert gpio + +Optional properties: +- status: Either "ok" or "disabled". + +Kirin960 Example: + kirin_pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpio = <&gpio11 1 0 >; + status = "ok"; + }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086bd67b..2406a54947df 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -156,5 +156,36 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + kirin_pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 + 0xf6000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpio = <&gpio11 1 0 >; + status = "ok"; + }; }; };
Add PCIe node for hi3660, and add binding documentation. Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com> --- .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++ 2 files changed, 83 insertions(+)