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[v7,2/4] arm64: dts: hisi: add kirin pcie node

Message ID 20170525030204.126233-3-songxiaowei@hisilicon.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Song Xiaowei May 25, 2017, 3:02 a.m. UTC
Add PCIe node for hi3660, and add binding documentation.

Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

Comments

Bjorn Helgaas May 30, 2017, 7:58 p.m. UTC | #1
On Thu, May 25, 2017 at 11:02:02AM +0800, Xiaowei Song wrote:
> Add PCIe node for hi3660, and add binding documentation.
> 
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3983086bd67b..8609e32ca46f 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -156,5 +156,36 @@
>  			clock-names = "uartclk", "apb_pclk";
>  			status = "disabled";
>  		};
> +
> +		pcie@f4000000 {
> +			compatible = "hisilicon,kirin960-pcie";
> +			reg =  <0x0 0xf4000000 0x0 0x1000>,
> +				<0x0 0xff3fe000 0x0 0x1000>,
> +				<0x0 0xf3f20000 0x0 0x40000>,
> +				<0x0 0xF5000000 0x0 0x2000>;

s/0xF5000000/0xf5000000/

Please indent these consistently so the cells line up, e.g.,

  reg = <0x0 0xf4000000 0x0  0x1000>,
	<0x0 0xff3fe000 0x0  0x1000>,
	<0x0 0xf3f20000 0x0 0x40000>,
	<0x0 0xf5000000 0x0  0x2000>;

> +			reg-names = "dbi", "apb", "phy", "config";
> +			bus-range = <0x0  0x1>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			device_type = "pci";
> +			ranges = <0x02000000 0x0 0x00000000 0x0
> +				0xf6000000 0x0 0x2000000>;
> +			num-lanes = <1>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0xf800 0 0 7>;
> +			interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
> +				<0x0 0 0 2 &gic 0 0 0  283 4>,
> +				<0x0 0 0 3 &gic 0 0 0  284 4>,
> +				<0x0 0 0 4 &gic 0 0 0  285 4>;
> +			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> +				<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +				<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +				<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +				<&crg_ctrl HI3660_ACLK_GATE_PCIE>;

Line up cells above.

> +			clock-names = "pcie_phy_ref", "pcie_aux",
> +				"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> +			reset-gpio = <&gpio11 1 0 >;
> +			status = "ok";
> +		};
>  	};
>  };
> -- 
> 2.11.GIT
>
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..8609e32ca46f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@ 
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
+
+		pcie@f4000000 {
+			compatible = "hisilicon,kirin960-pcie";
+			reg =  <0x0 0xf4000000 0x0 0x1000>,
+				<0x0 0xff3fe000 0x0 0x1000>,
+				<0x0 0xf3f20000 0x0 0x40000>,
+				<0x0 0xF5000000 0x0 0x2000>;
+			reg-names = "dbi", "apb", "phy", "config";
+			bus-range = <0x0  0x1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x02000000 0x0 0x00000000 0x0
+				0xf6000000 0x0 0x2000000>;
+			num-lanes = <1>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+				<0x0 0 0 2 &gic 0 0 0  283 4>,
+				<0x0 0 0 3 &gic 0 0 0  284 4>,
+				<0x0 0 0 4 &gic 0 0 0  285 4>;
+			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+				<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+				<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+				<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+				<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+			clock-names = "pcie_phy_ref", "pcie_aux",
+				"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+			reset-gpio = <&gpio11 1 0 >;
+			status = "ok";
+		};
 	};
 };