@@ -205,6 +205,16 @@ static bool pcie_retrain_link(struct pcie_link_state *link)
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
reg16 |= PCI_EXP_LNKCTL_RL;
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
+ if (parent->clear_retrain_link) {
+ /*
+ * Due to an erratum in some devices the retrain link bit
+ * needs to be cleared again manually to allow the link
+ * training to succeed.
+ */
+ reg16 &= ~PCI_EXP_LNKCTL_RL;
+ pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
+ pci_info(parent, "Apply PCIe clear link retrain bit workaround\n");
+ }
/* Wait for link training end. Break out after waiting for timeout */
start_jiffies = jiffies;
@@ -2245,6 +2245,26 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
+#ifdef CONFIG_PCIEASPM
+/*
+ * Some Pericom PCIe-to-PCI bridges in reverse mode expose the erratum that
+ * they need the PCIe link retrain bit cleared after starting the link retrain
+ * process to allow this process to finish.
+ *
+ * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130
+ *
+ * See also the Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
+ */
+static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
+{
+ dev->clear_retrain_link = 1;
+ pci_info(dev, "Enable PCIe link retrain quirk\n");
+}
+DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
+DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
+DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
+#endif /* CONFIG_PCIEASPM */
+
static void fixup_rev1_53c810(struct pci_dev *dev)
{
u32 class = dev->class;
@@ -355,6 +355,8 @@ struct pci_dev {
struct pcie_link_state *link_state; /* ASPM link state */
unsigned int ltr_path:1; /* Latency Tolerance Reporting
supported from root to here */
+ unsigned int clear_retrain_link:1; /* Need to clear link retrain
+ bit to succeed retraining */
#endif
unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
Due to an erratum in some Pericom PCIe-to-PCI bridges in reverse mode the retrain link bit needs to be cleared again manually to allow the link training to complete successfully. If it is not cleared manually the link training is continuously restarted and all devices below the PCI-to-PCIe bridge can't be accessed any more. That means drivers for devices below the bridge will be loaded but won't work or even crash because the driver is only reading 0xffff. See the Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf for details. Devices known as affected so far are: PI7C9X110, PI7C9X111SL, PI7C9X130 The patch introduces a new flag clear_retrain_link in the struct pci_dev. This flag is set in quirk_enable_clear_retrain_link() for the affected devices in the pci_fixup_header in quirks.c In preparation to this patch the link retraining code was moved to pcie_retrain_link(). This function now applies the work around to clear the PCI_EXP_LNKCTL_RL bit again if clear_retrain_link bit is set in the pci_dev structure of the link parent device. Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu> --- drivers/pci/pcie/aspm.c | 10 ++++++++++ drivers/pci/quirks.c | 20 ++++++++++++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 32 insertions(+)