@@ -204,7 +204,9 @@
#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff
#define RP_VEND_XP 0x00000f00
-#define RP_VEND_XP_DL_UP (1 << 30)
+#define RP_VEND_XP_DL_UP (1 << 30)
+#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
+#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
#define RP_VEND_CTL1 0x00000f48
#define RP_VEND_CTL1_ERPT (1 << 13)
@@ -529,6 +531,12 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
value = readl(port->base + RP_VEND_CTL1);
value |= RP_VEND_CTL1_ERPT;
writel(value, port->base + RP_VEND_CTL1);
+
+ /* Optimal settings to enhance bandwidth */
+ value = readl(port->base + RP_VEND_XP);
+ value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
+ value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
+ writel(value, port->base + RP_VEND_XP);
}
static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)