@@ -323,6 +323,7 @@ struct tegra_pcie_soc {
bool program_deskew_time;
bool raw_violation_fixup;
bool update_fc_timer;
+ bool has_cache_bars;
struct {
struct {
u32 rp_ectl_2_r1;
@@ -932,11 +933,13 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
afi_writel(pcie, 0, AFI_FPCI_BAR5);
- /* map all upstream transactions as uncached */
- afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
- afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
- afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
- afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
+ if (pcie->soc->has_cache_bars) {
+ /* map all upstream transactions as uncached */
+ afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
+ afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
+ afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
+ afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
+ }
/* MSI translations are setup only when needed */
afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
@@ -2441,6 +2444,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.program_deskew_time = false,
.raw_violation_fixup = false,
.update_fc_timer = false,
+ .has_cache_bars = true,
.ectl.enable = false,
};
@@ -2469,6 +2473,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.program_deskew_time = false,
.raw_violation_fixup = false,
.update_fc_timer = false,
+ .has_cache_bars = false,
.ectl.enable = false,
};
@@ -2492,6 +2497,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.program_deskew_time = false,
.raw_violation_fixup = true,
.update_fc_timer = false,
+ .has_cache_bars = false,
.ectl.enable = false,
};
@@ -2515,6 +2521,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.program_deskew_time = true,
.raw_violation_fixup = false,
.update_fc_timer = true,
+ .has_cache_bars = false,
.ectl = {
.regs = {
.rp_ectl_2_r1 = 0x0000000f,
@@ -2555,6 +2562,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.program_deskew_time = false,
.raw_violation_fixup = false,
.update_fc_timer = false,
+ .has_cache_bars = false,
.ectl.enable = false,
};