[v3,17/17] PCI: Lower PCIE_RESET_READY_POLL_MS from 1m to 1s

Commit Message

Stanislav Spassov March 3, 2020, 1:28 p.m. UTC

From: Stanislav Spassov <[e-mail]>

PCI Express Base specification r5.0 (May 22, 2019), sec 6.6.1 mentions
on more than one occasion that the appropriate waiting time before
deeming a device broken if it is not able to return Successful
Completion for valid Configuration Requests is 1 second after a
Conventional Reset (which should be the lengthiest of resets).

For devices that take longer than 1s to complete initialization, quirks
can override the waiting time via the reset_ready_poll_ms field in
struct pci_dev.

Note: This timeout is used in pci_dev_wait for the polling that happens
after we have already waited for the required post-reset times mandated
by the spec. All devices are expected to be responsive to Configuration
Requests at that point. "Completing initialization" here means that the
device is not only responsive, but actually returns Successful
Completions rather than CRS Completions (or any other error).

Signed-off-by: Stanislav Spassov <[e-mail]>
---
 drivers/pci/pci.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Patch

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d8043d4dbe2f..1c6722b5c3ee 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -113,8 +113,11 @@  int pci_bus_error_reset(struct pci_dev *dev);
 /* D0/D1->D2 and D2->D0 delay */
 #define PCI_PM_D2_DELAY		200
 
-/* Time to wait after a reset for device to become responsive */
-#define PCIE_RESET_READY_POLL_MS 60000
+/*
+ * Time to wait (in addition to the delays above) for a device to start
+ * returning Successful Completions before OS can deem it broken
+ */
+#define PCIE_RESET_READY_POLL_MS 1000
 
 /**
  * struct pci_platform_pm_ops - Firmware PM callbacks