Message ID | 20200907053801.22149-7-Zhiqiang.Hou@nxp.com (mailing list archive) |
---|---|
State | Superseded, archived |
Delegated to: | Lorenzo Pieralisi |
Headers | show |
Series | PCI: layerscape: Add power management support | expand |
On Mon, Sep 07, 2020 at 01:38:00PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > The LS1043A PCIe controller has some control registers > in SCFG block, so add the SCFG phandle for each PCIe > controller DT node. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> 'arm64: dts: ...' for subject prefix. Shawn
Hi Shawn, Thanks a lot for your comments! > -----Original Message----- > From: Shawn Guo <shawnguo@kernel.org> > Sent: 2020年9月21日 21:17 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; bhelgaas@google.com; robh+dt@kernel.org; > Leo Li <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com; > gustavo.pimentel@synopsys.com; M.h. Lian <minghuan.lian@nxp.com>; > Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com> > Subject: Re: [PATCH 6/7] dts: arm64: ls1043a: Add SCFG phandle for PCIe > nodes > > On Mon, Sep 07, 2020 at 01:38:00PM +0800, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > The LS1043A PCIe controller has some control registers in SCFG block, > > so add the SCFG phandle for each PCIe controller DT node. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > 'arm64: dts: ...' for subject prefix. Will correct it in next version. Regards, Zhiqiang > > Shawn
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 70e07612da12..30ccf1fdb851 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -822,6 +822,7 @@ interrupts = <0 118 0x4>, /* controller interrupt */ <0 117 0x4>; /* PME interrupt */ interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -849,6 +850,7 @@ interrupts = <0 128 0x4>, <0 127 0x4>; interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -876,6 +878,7 @@ interrupts = <0 162 0x4>, <0 161 0x4>; interrupt-names = "intr", "pme"; + fsl,pcie-scfg = <&scfg 2>; #address-cells = <3>; #size-cells = <2>; device_type = "pci";