| Message ID | 20201024205548.1837770-2-ian.kumlien@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [1/3] PCI/ASPM: Use the path max in L1 ASPM latency check | expand |
*bump* On Sat, Oct 24, 2020 at 10:55 PM Ian Kumlien <ian.kumlien@gmail.com> wrote: > > From what I have been able to figure out, it seems like LOs path latency > is cumulative, so the max path latency should be the sum of all links > maximum latency. > > Signed-off-by: Ian Kumlien <ian.kumlien@gmail.com> > --- > drivers/pci/pcie/aspm.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > index c03ead0f1013..dbe3ce60c1ff 100644 > --- a/drivers/pci/pcie/aspm.c > +++ b/drivers/pci/pcie/aspm.c > @@ -434,7 +434,8 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, > > static void pcie_aspm_check_latency(struct pci_dev *endpoint) > { > - u32 latency, l1_max_latency = 0, l1_switch_latency = 0; > + u32 latency, l1_max_latency = 0, l1_switch_latency = 0, > + l0s_latency_up = 0, l0s_latency_dw = 0; > struct aspm_latency *acceptable; > struct pcie_link_state *link; > > @@ -448,14 +449,18 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) > > while (link) { > /* Check upstream direction L0s latency */ > - if ((link->aspm_capable & ASPM_STATE_L0S_UP) && > - (link->latency_up.l0s > acceptable->l0s)) > - link->aspm_capable &= ~ASPM_STATE_L0S_UP; > + if (link->aspm_capable & ASPM_STATE_L0S_UP) { > + l0s_latency_up += link->latency_up.l0s; > + if (l0s_latency_up > acceptable->l0s) > + link->aspm_capable &= ~ASPM_STATE_L0S_UP; > + } > > /* Check downstream direction L0s latency */ > - if ((link->aspm_capable & ASPM_STATE_L0S_DW) && > - (link->latency_dw.l0s > acceptable->l0s)) > - link->aspm_capable &= ~ASPM_STATE_L0S_DW; > + if (link->aspm_capable & ASPM_STATE_L0S_DW) { > + l0s_latency_dw += link->latency_dw.l0s; > + if (l0s_latency_dw > acceptable->l0s) > + link->aspm_capable &= ~ASPM_STATE_L0S_DW; > + } > > /* > * Check L1 latency. > -- > 2.29.1 >
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index c03ead0f1013..dbe3ce60c1ff 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -434,7 +434,8 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev, static void pcie_aspm_check_latency(struct pci_dev *endpoint) { - u32 latency, l1_max_latency = 0, l1_switch_latency = 0; + u32 latency, l1_max_latency = 0, l1_switch_latency = 0, + l0s_latency_up = 0, l0s_latency_dw = 0; struct aspm_latency *acceptable; struct pcie_link_state *link; @@ -448,14 +449,18 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) while (link) { /* Check upstream direction L0s latency */ - if ((link->aspm_capable & ASPM_STATE_L0S_UP) && - (link->latency_up.l0s > acceptable->l0s)) - link->aspm_capable &= ~ASPM_STATE_L0S_UP; + if (link->aspm_capable & ASPM_STATE_L0S_UP) { + l0s_latency_up += link->latency_up.l0s; + if (l0s_latency_up > acceptable->l0s) + link->aspm_capable &= ~ASPM_STATE_L0S_UP; + } /* Check downstream direction L0s latency */ - if ((link->aspm_capable & ASPM_STATE_L0S_DW) && - (link->latency_dw.l0s > acceptable->l0s)) - link->aspm_capable &= ~ASPM_STATE_L0S_DW; + if (link->aspm_capable & ASPM_STATE_L0S_DW) { + l0s_latency_dw += link->latency_dw.l0s; + if (l0s_latency_dw > acceptable->l0s) + link->aspm_capable &= ~ASPM_STATE_L0S_DW; + } /* * Check L1 latency.
From what I have been able to figure out, it seems like LOs path latency is cumulative, so the max path latency should be the sum of all links maximum latency. Signed-off-by: Ian Kumlien <ian.kumlien@gmail.com> --- drivers/pci/pcie/aspm.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)