| Message ID | 20201224094500.19149-3-daire.mcnamara@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: microchip: Add host driver for Microchip PCIe controller | expand |
On 2020-12-24 09:44, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > Add device tree bindings for the Microchip PolarFire PCIe controller > when configured in host (Root Complex) mode. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../bindings/pci/microchip,pcie-host.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > > diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > new file mode 100644 > index 000000000000..5a56f07a5ceb > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings > + > +maintainers: > + - Daire McNamara <daire.mcnamara@microchip.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + const: microchip,pcie-host-1.0 # PolarFire > + > + reg: > + maxItems: 2 > + > + reg-names: > + items: > + - const: cfg > + - const: apb > + > + interrupts: > + minItems: 1 > + maxItems: 2 > + items: > + - description: PCIe host controller > + - description: builtin MSI controller > + > + interrupt-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: pcie > + - const: msi > + > + ranges: > + maxItems: 1 > + > + msi-controller: > + description: Identifies the node as an MSI controller. > + > + msi-parent: > + description: MSI controller the device is capable of using. > + > +required: > + - reg > + - reg-names > + - "#interrupt-cells" > + - interrupts > + - interrupt-map-mask > + - interrupt-map > + - msi-controller > + > +unevaluatedProperties: false > + > +examples: > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + pcie0: pcie@2030000000 { > + compatible = "microchip,pcie-host-1.0"; > + reg = <0x0 0x70000000 0x0 0x08000000>, > + <0x0 0x43000000 0x0 0x00010000>; > + reg-names = "cfg", "apb"; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + interrupts = <119>; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0 0 0 1 &pcie_intc0 0>, > + <0 0 0 2 &pcie_intc0 1>, > + <0 0 0 3 &pcie_intc0 2>, > + <0 0 0 4 &pcie_intc0 3>; > + interrupt-parent = <&plic0>; > + msi-parent = <&pcie0>; > + msi-controller; > + bus-range = <0x00 0x7f>; > + ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; > + pcie_intc_0: interrupt-controller { Very minor nitpick, the name here doesn't match the one in interrupt-map, there is an extra '_'. Otherwise I have tested this patch series on top of Atish's tree, and it works fine with a NVME device. Tested-by: Aurelien Jarno <aurelien@aurel32.net> Aurelien
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml new file mode 100644 index 000000000000..5a56f07a5ceb --- /dev/null +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings + +maintainers: + - Daire McNamara <daire.mcnamara@microchip.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: microchip,pcie-host-1.0 # PolarFire + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: apb + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: PCIe host controller + - description: builtin MSI controller + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + - const: pcie + - const: msi + + ranges: + maxItems: 1 + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + +required: + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-map-mask + - interrupt-map + - msi-controller + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie0: pcie@2030000000 { + compatible = "microchip,pcie-host-1.0"; + reg = <0x0 0x70000000 0x0 0x08000000>, + <0x0 0x43000000 0x0 0x00010000>; + reg-names = "cfg", "apb"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupts = <119>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + interrupt-parent = <&plic0>; + msi-parent = <&pcie0>; + msi-controller; + bus-range = <0x00 0x7f>; + ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };