Message ID | 20210623100525.19944-4-omp@nvidia.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Lorenzo Pieralisi |
Headers | show
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Wed, 23 Jun 2021 10:05:45 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 23 Jun 2021 10:05:44 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 23 Jun 2021 10:05:40 +0000 From: Om Prakash Singh <omp@nvidia.com> To: <kw@linux.com>, <helgaas@kernel.org>, <vidyas@nvidia.com>, <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com> CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, Om Prakash Singh <omp@nvidia.com> Subject: [PATCH V3 3/5] PCI: tegra194: Disable interrupts before entering L2 Date: Wed, 23 Jun 2021 15:35:23 +0530 Message-ID: <20210623100525.19944-4-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210623100525.19944-1-omp@nvidia.com> References: <20210623100525.19944-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98f46072-b366-4f19-a623-08d9362e7783 X-MS-TrafficTypeDiagnostic: BY5PR12MB3666: X-Microsoft-Antispam-PRVS: <BY5PR12MB366659FE2D928B2AD766888ADA089@BY5PR12MB3666.namprd12.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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Series |
Update pcie-tegra194 driver
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expand
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diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 66e00b276cd3..64ec0da31b5b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1593,6 +1593,16 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) return; } + /* + * PCIe controller exits from L2 only if reset is applied, so + * controller doesn't handle interrupts. But in cases where + * L2 entry fails, PERST# is asserted which can trigger surprise + * link down AER. However this function call happens in + * suspend_noirq(), so AER interrupt will not be processed. + * Disable all interrupts to avoid such a scenario. + */ + appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0); + if (tegra_pcie_try_link_l2(pcie)) { dev_info(pcie->dev, "Link didn't transition to L2 state\n"); /*