diff mbox series

PCI: Add ACS quirk for Cavium multi-function devices

Message ID 20210810122425.1115156-1-george.cherian@marvell.com (mailing list archive)
State Accepted
Delegated to: Bjorn Helgaas
Headers show
Series PCI: Add ACS quirk for Cavium multi-function devices | expand

Commit Message

George Cherian Aug. 10, 2021, 12:24 p.m. UTC
Some Cavium endpoints are implemented as multi-function devices
without ACS capability, but they actually don't support peer-to-peer
transactions.

Add ACS quirks to declare DMA isolation.

Apply te quirk for following devices
1. BGX device found on Octeon-TX (8xxx)
2. CGX device found on Octeon-TX2 (9xxx)
3. RPM device found on Octeon-TX3 (10xxx)

Signed-off-by: George Cherian <george.cherian@marvell.com>
---
 drivers/pci/quirks.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Bjorn Helgaas Aug. 10, 2021, 2:47 p.m. UTC | #1
On Tue, Aug 10, 2021 at 05:54:25PM +0530, George Cherian wrote:
> Some Cavium endpoints are implemented as multi-function devices
> without ACS capability, but they actually don't support peer-to-peer
> transactions.
> 
> Add ACS quirks to declare DMA isolation.
> 
> Apply te quirk for following devices
> 1. BGX device found on Octeon-TX (8xxx)
> 2. CGX device found on Octeon-TX2 (9xxx)
> 3. RPM device found on Octeon-TX3 (10xxx)
> 
> Signed-off-by: George Cherian <george.cherian@marvell.com>
> ---
>  drivers/pci/quirks.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 6d74386eadc2..076932018494 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -4840,6 +4840,10 @@ static const struct pci_dev_acs_enabled {
>  	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
>  	/* Cavium ThunderX */
>  	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
> +	/* Cavium multi-function devices */
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },

Is there a plan to add ACS capabilities to future devices, or is
Cavium just resigned to forever adding and backporting quirks?

>  	/* APM X-Gene */
>  	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
>  	/* Ampere Computing */
> -- 
> 2.25.1
>
Bjorn Helgaas Aug. 20, 2021, 9:14 p.m. UTC | #2
On Tue, Aug 10, 2021 at 05:54:25PM +0530, George Cherian wrote:
> Some Cavium endpoints are implemented as multi-function devices
> without ACS capability, but they actually don't support peer-to-peer
> transactions.
> 
> Add ACS quirks to declare DMA isolation.
> 
> Apply te quirk for following devices
> 1. BGX device found on Octeon-TX (8xxx)
> 2. CGX device found on Octeon-TX2 (9xxx)
> 3. RPM device found on Octeon-TX3 (10xxx)
> 
> Signed-off-by: George Cherian <george.cherian@marvell.com>

Applied to pci/virtualization for v5.15, thanks!

> ---
>  drivers/pci/quirks.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 6d74386eadc2..076932018494 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -4840,6 +4840,10 @@ static const struct pci_dev_acs_enabled {
>  	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
>  	/* Cavium ThunderX */
>  	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
> +	/* Cavium multi-function devices */
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
> +	{ PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
>  	/* APM X-Gene */
>  	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
>  	/* Ampere Computing */
> -- 
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6d74386eadc2..076932018494 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4840,6 +4840,10 @@  static const struct pci_dev_acs_enabled {
 	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
 	/* Cavium ThunderX */
 	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
+	/* Cavium multi-function devices */
+	{ PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
+	{ PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
+	{ PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
 	/* APM X-Gene */
 	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
 	/* Ampere Computing */