| Message ID | 20210917024648.1383476-1-kuba@kernel.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [v2] x86/intel: Disable HPET on another Intel Coffee Lake platform | expand |
Hi Jakub, > My Lenovo T490s with i7-8665U had been marking TSC as unstable > since v5.13, resulting in very sluggish desktop experience... > > Kernel logs show: > > clocksource: timekeeping watchdog on CPU3: hpet read-back delay of 316000ns, attempt 4, marking unstable > tsc: Marking TSC unstable due to clocksource watchdog > TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. > sched_clock: Marking unstable (14539801827657, -530891666)<-(14539319241737, -48307500) > clocksource: Checking clocksource tsc synchronization from CPU 3 to CPUs 0-2,6-7. > clocksource: Switched to clocksource hpet > > I have a 8086:3e34 bridge, also known as "Host bridge: Intel > Corporation Coffee Lake HOST and DRAM Controller (rev 0c)". > Add it to the list. > > We should perhaps consider applying this quirk more widely. > The Intel documentation does not list my device [1], but > linuxhw [2] does, and it seems to list a few more bridges > we do not currently cover (3e31, 3ecc, 3e35, 3e0f). I wish someone from Intel would be a little more forthcoming and chimed in about the other devices. I guess, we will cross that bridge when we get to it, so to speak. > [1] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8th-gen-core-family-datasheet-vol-2.pdf > [2] https://github.com/linuxhw/DevicePopulation/blob/master/README.md > > Cc: stable@vger.kernel.org # v5.13+ > Signed-off-by: Jakub Kicinski <kuba@kernel.org> > --- > v2: - add the dmesg output > --- > arch/x86/kernel/early-quirks.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c > index 38837dad46e6..7d2de04f8750 100644 > --- a/arch/x86/kernel/early-quirks.c > +++ b/arch/x86/kernel/early-quirks.c > @@ -716,6 +716,8 @@ static struct chipset early_qrk[] __initdata = { > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x3e20, > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > + { PCI_VENDOR_ID_INTEL, 0x3e34, > + PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x3ec4, > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x8a12, Thank you! Acked-by: Krzysztof Wilczyński <kw@linux.com> Krzysztof
On Thu, 16 Sep 2021 19:46:48 -0700 Jakub Kicinski wrote: > My Lenovo T490s with i7-8665U had been marking TSC as unstable > since v5.13, resulting in very sluggish desktop experience... Where do we stand? Waiting for tglx to refactor PC10 detection and use that, or just review delay? > +++ b/arch/x86/kernel/early-quirks.c > @@ -716,6 +716,8 @@ static struct chipset early_qrk[] __initdata = { > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x3e20, > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > + { PCI_VENDOR_ID_INTEL, 0x3e34, > + PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x3ec4, > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > { PCI_VENDOR_ID_INTEL, 0x8a12,
On Wed, Sep 29, 2021 at 06:11:07AM -0700, Jakub Kicinski wrote: > On Thu, 16 Sep 2021 19:46:48 -0700 Jakub Kicinski wrote: > > My Lenovo T490s with i7-8665U had been marking TSC as unstable > > since v5.13, resulting in very sluggish desktop experience... > > Where do we stand? Waiting for tglx to refactor PC10 detection and use > that, or just review delay? From my point of view, this is an x86 issue, not a PCI one, so I'll defer to the x86 folks. > > +++ b/arch/x86/kernel/early-quirks.c > > @@ -716,6 +716,8 @@ static struct chipset early_qrk[] __initdata = { > > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > > { PCI_VENDOR_ID_INTEL, 0x3e20, > > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > > + { PCI_VENDOR_ID_INTEL, 0x3e34, > > + PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > > { PCI_VENDOR_ID_INTEL, 0x3ec4, > > PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, > > { PCI_VENDOR_ID_INTEL, 0x8a12, >
On Wed, Sep 29 2021 at 11:05, Bjorn Helgaas wrote: > On Wed, Sep 29, 2021 at 06:11:07AM -0700, Jakub Kicinski wrote: >> On Thu, 16 Sep 2021 19:46:48 -0700 Jakub Kicinski wrote: >> > My Lenovo T490s with i7-8665U had been marking TSC as unstable >> > since v5.13, resulting in very sluggish desktop experience... >> >> Where do we stand? Waiting for tglx to refactor PC10 detection and use >> that, or just review delay? > > From my point of view, this is an x86 issue, not a PCI one, so I'll > defer to the x86 folks. Yes, it is. I'm still trying to make sense of this enumeration muck. Adding these silly PCI ids to the quirks section is a whack a mole game which does not make sense. Lemme find a few spare cycles to whip up a patch. Thanks, tglx
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 38837dad46e6..7d2de04f8750 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -716,6 +716,8 @@ static struct chipset early_qrk[] __initdata = { PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, { PCI_VENDOR_ID_INTEL, 0x3e20, PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, + { PCI_VENDOR_ID_INTEL, 0x3e34, + PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, { PCI_VENDOR_ID_INTEL, 0x3ec4, PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, { PCI_VENDOR_ID_INTEL, 0x8a12,
My Lenovo T490s with i7-8665U had been marking TSC as unstable since v5.13, resulting in very sluggish desktop experience... Kernel logs show: clocksource: timekeeping watchdog on CPU3: hpet read-back delay of 316000ns, attempt 4, marking unstable tsc: Marking TSC unstable due to clocksource watchdog TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'. sched_clock: Marking unstable (14539801827657, -530891666)<-(14539319241737, -48307500) clocksource: Checking clocksource tsc synchronization from CPU 3 to CPUs 0-2,6-7. clocksource: Switched to clocksource hpet I have a 8086:3e34 bridge, also known as "Host bridge: Intel Corporation Coffee Lake HOST and DRAM Controller (rev 0c)". Add it to the list. We should perhaps consider applying this quirk more widely. The Intel documentation does not list my device [1], but linuxhw [2] does, and it seems to list a few more bridges we do not currently cover (3e31, 3ecc, 3e35, 3e0f). [1] https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8th-gen-core-family-datasheet-vol-2.pdf [2] https://github.com/linuxhw/DevicePopulation/blob/master/README.md Cc: stable@vger.kernel.org # v5.13+ Signed-off-by: Jakub Kicinski <kuba@kernel.org> --- v2: - add the dmesg output --- arch/x86/kernel/early-quirks.c | 2 ++ 1 file changed, 2 insertions(+)