| Message ID | 20211218141024.500952-2-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | qcom: add support for PCIe on SM8450 platform | expand |
On Sat, Dec 18, 2021 at 05:10:20PM +0300, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > different set of clocks, so two compatible entries are required. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > index a0ae024c2d0c..0adb56d5645e 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > @@ -15,6 +15,8 @@ > - "qcom,pcie-sc8180x" for sc8180x > - "qcom,pcie-sdm845" for sdm845 > - "qcom,pcie-sm8250" for sm8250 > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 What's the difference between the two? > - "qcom,pcie-ipq6018" for ipq6018 > > - reg: > @@ -169,6 +171,24 @@ > - "ddrss_sf_tbu" PCIe SF TBU clock > - "pipe" PIPE clock > > +- clock-names: > + Usage: required for sm8450-pcie0 and sm8450-pcie1 > + Value type: <stringlist> > + Definition: Should contain the following entries > + - "aux" Auxiliary clock > + - "cfg" Configuration clock > + - "bus_master" Master AXI clock > + - "bus_slave" Slave AXI clock > + - "slave_q2a" Slave Q2A clock > + - "tbu" PCIe TBU clock > + - "ddrss_sf_tbu" PCIe SF TBU clock > + - "pipe" PIPE clock > + - "pipe_mux" PIPE MUX > + - "phy_pipe" PIPE output clock > + - "ref" REFERENCE clock > + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 > + - "aggre1" Aggre NoC PCIe1 AXI clock > + > - resets: > Usage: required > Value type: <prop-encoded-array> > @@ -246,7 +266,7 @@ > - "ahb" AHB reset > > - reset-names: > - Usage: required for sc8180x, sdm845 and sm8250 > + Usage: required for sc8180x, sdm845, sm8250 and sm8450 > Value type: <stringlist> > Definition: Should contain the following entries > - "pci" PCIe core reset > -- > 2.34.1 > >
On Tue, 21 Dec 2021 at 17:59, Rob Herring <robh@kernel.org> wrote: > > On Sat, Dec 18, 2021 at 05:10:20PM +0300, Dmitry Baryshkov wrote: > > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > > different set of clocks, so two compatible entries are required. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > index a0ae024c2d0c..0adb56d5645e 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > @@ -15,6 +15,8 @@ > > - "qcom,pcie-sc8180x" for sc8180x > > - "qcom,pcie-sdm845" for sdm845 > > - "qcom,pcie-sm8250" for sm8250 > > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > > What's the difference between the two? Clocks used by these hosts. Quoting the definition: + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 + - "aggre1" Aggre NoC PCIe1 AXI clock aggre1 is used by both pcie0 and pcie1, while aggre0 is used only by pcie0. > > > - "qcom,pcie-ipq6018" for ipq6018 > > > > - reg: > > @@ -169,6 +171,24 @@ > > - "ddrss_sf_tbu" PCIe SF TBU clock > > - "pipe" PIPE clock > > > > +- clock-names: > > + Usage: required for sm8450-pcie0 and sm8450-pcie1 > > + Value type: <stringlist> > > + Definition: Should contain the following entries > > + - "aux" Auxiliary clock > > + - "cfg" Configuration clock > > + - "bus_master" Master AXI clock > > + - "bus_slave" Slave AXI clock > > + - "slave_q2a" Slave Q2A clock > > + - "tbu" PCIe TBU clock > > + - "ddrss_sf_tbu" PCIe SF TBU clock > > + - "pipe" PIPE clock > > + - "pipe_mux" PIPE MUX > > + - "phy_pipe" PIPE output clock > > + - "ref" REFERENCE clock > > + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 > > + - "aggre1" Aggre NoC PCIe1 AXI clock > > + > > - resets: > > Usage: required > > Value type: <prop-encoded-array> > > @@ -246,7 +266,7 @@ > > - "ahb" AHB reset > > > > - reset-names: > > - Usage: required for sc8180x, sdm845 and sm8250 > > + Usage: required for sc8180x, sdm845, sm8250 and sm8450 > > Value type: <stringlist> > > Definition: Should contain the following entries > > - "pci" PCIe core reset > > -- > > 2.34.1 > > > >
On Tue, Dec 21, 2021 at 06:43:31PM +0300, Dmitry Baryshkov wrote: > On Tue, 21 Dec 2021 at 17:59, Rob Herring <robh@kernel.org> wrote: > > > > On Sat, Dec 18, 2021 at 05:10:20PM +0300, Dmitry Baryshkov wrote: > > > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > > > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > > > different set of clocks, so two compatible entries are required. > > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > --- > > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > index a0ae024c2d0c..0adb56d5645e 100644 > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > @@ -15,6 +15,8 @@ > > > - "qcom,pcie-sc8180x" for sc8180x > > > - "qcom,pcie-sdm845" for sdm845 > > > - "qcom,pcie-sm8250" for sm8250 > > > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > > > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > > > > What's the difference between the two? > > Clocks used by these hosts. Quoting the definition: > > + - "aggre0" Aggre NoC PCIe0 AXI clock, only > for sm8450-pcie0 > + - "aggre1" Aggre NoC PCIe1 AXI clock > > aggre1 is used by both pcie0 and pcie1, while aggre0 is used only by pcie0. That doesn't really seem like you need a different compatible for that. Do you need to handle them differently? It seems like abuse of clocks putting bus/interconnect clocks here, but sadly that's all too common. Rob
On Tue, 21 Dec 2021 at 22:52, Rob Herring <robh@kernel.org> wrote: > > On Tue, Dec 21, 2021 at 06:43:31PM +0300, Dmitry Baryshkov wrote: > > On Tue, 21 Dec 2021 at 17:59, Rob Herring <robh@kernel.org> wrote: > > > > > > On Sat, Dec 18, 2021 at 05:10:20PM +0300, Dmitry Baryshkov wrote: > > > > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > > > > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > > > > different set of clocks, so two compatible entries are required. > > > > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > > --- > > > > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > > > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > index a0ae024c2d0c..0adb56d5645e 100644 > > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > > > > @@ -15,6 +15,8 @@ > > > > - "qcom,pcie-sc8180x" for sc8180x > > > > - "qcom,pcie-sdm845" for sdm845 > > > > - "qcom,pcie-sm8250" for sm8250 > > > > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > > > > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > > > > > > What's the difference between the two? > > > > Clocks used by these hosts. Quoting the definition: > > > > + - "aggre0" Aggre NoC PCIe0 AXI clock, only > > for sm8450-pcie0 > > + - "aggre1" Aggre NoC PCIe1 AXI clock > > > > aggre1 is used by both pcie0 and pcie1, while aggre0 is used only by pcie0. > > That doesn't really seem like you need a different compatible for that. > Do you need to handle them differently? It seems like abuse of clocks > putting bus/interconnect clocks here, but sadly that's all too common. Unfortunately, yes, it looks like we need to handle them differently. The clocks are not handled by the interconnect on their own.
On Sat, 18 Dec 2021 17:10:20 +0300, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > different set of clocks, so two compatible entries are required. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Sat 18 Dec 06:10 PST 2021, Dmitry Baryshkov wrote: > Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar > to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use > different set of clocks, so two compatible entries are required. > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > index a0ae024c2d0c..0adb56d5645e 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt > @@ -15,6 +15,8 @@ > - "qcom,pcie-sc8180x" for sc8180x > - "qcom,pcie-sdm845" for sdm845 > - "qcom,pcie-sm8250" for sm8250 > + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 > + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 > - "qcom,pcie-ipq6018" for ipq6018 > > - reg: > @@ -169,6 +171,24 @@ > - "ddrss_sf_tbu" PCIe SF TBU clock > - "pipe" PIPE clock > > +- clock-names: > + Usage: required for sm8450-pcie0 and sm8450-pcie1 > + Value type: <stringlist> > + Definition: Should contain the following entries > + - "aux" Auxiliary clock > + - "cfg" Configuration clock > + - "bus_master" Master AXI clock > + - "bus_slave" Slave AXI clock > + - "slave_q2a" Slave Q2A clock > + - "tbu" PCIe TBU clock > + - "ddrss_sf_tbu" PCIe SF TBU clock > + - "pipe" PIPE clock > + - "pipe_mux" PIPE MUX > + - "phy_pipe" PIPE output clock > + - "ref" REFERENCE clock > + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 > + - "aggre1" Aggre NoC PCIe1 AXI clock > + > - resets: > Usage: required > Value type: <prop-encoded-array> > @@ -246,7 +266,7 @@ > - "ahb" AHB reset > > - reset-names: > - Usage: required for sc8180x, sdm845 and sm8250 > + Usage: required for sc8180x, sdm845, sm8250 and sm8450 > Value type: <stringlist> > Definition: Should contain the following entries > - "pci" PCIe core reset > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..0adb56d5645e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -15,6 +15,8 @@ - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - "qcom,pcie-ipq6018" for ipq6018 - reg: @@ -169,6 +171,24 @@ - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock +- clock-names: + Usage: required for sm8450-pcie0 and sm8450-pcie1 + Value type: <stringlist> + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_mux" PIPE MUX + - "phy_pipe" PIPE output clock + - "ref" REFERENCE clock + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 + - "aggre1" Aggre NoC PCIe1 AXI clock + - resets: Usage: required Value type: <prop-encoded-array> @@ -246,7 +266,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8250 and sm8450 Value type: <stringlist> Definition: Should contain the following entries - "pci" PCIe core reset
Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use different set of clocks, so two compatible entries are required. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)