@@ -336,6 +336,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)
struct dw_edma_desc *desc;
u32 cnt = 0;
int i;
+ bool b;
if (!chan->configured)
return NULL;
@@ -424,7 +425,11 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer)
chunk->ll_region.sz += burst->sz;
desc->alloc_sz += burst->sz;
- if (chan->dir == EDMA_DIR_WRITE) {
+ b = (chan->dir == EDMA_DIR_WRITE);
+ if (chan->chip->flags & DW_EDMA_CHIP_LOCAL_EP)
+ b = !b;
+
+ if (b) {
burst->sar = src_addr;
if (xfer->type == EDMA_XFER_CYCLIC) {
burst->dar = xfer->xfer.cyclic.paddr;
@@ -301,13 +301,18 @@ u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
{
struct dw_edma_burst *child;
+ struct dw_edma_chan *chan = chunk->chan;
struct dw_edma_v0_lli __iomem *lli;
struct dw_edma_v0_llp __iomem *llp;
u32 control = 0, i = 0;
+ u32 rie = 0;
int j;
lli = chunk->ll_region.vaddr;
+ if (!(chan->chip->flags & DW_EDMA_CHIP_NO_MSI))
+ rie = DW_EDMA_V0_RIE;
+
if (chunk->cb)
control = DW_EDMA_V0_CB;
@@ -315,7 +320,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
list_for_each_entry(child, &chunk->burst->list, list) {
j--;
if (!j)
- control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE);
+ control |= (DW_EDMA_V0_LIE | rie);
/* Channel control */
SET_LL_32(&lli[i].control, control);
@@ -414,15 +419,17 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
SET_CH_32(dw, chan->dir, chan->id, ch_control1,
(DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
/* Linked list */
- #ifdef CONFIG_64BIT
+
+ if (!(chan->chip->flags & DW_EDMA_CHIP_REG32BIT) &&
+ IS_ENABLED(CONFIG_64BIT)) {
SET_CH_64(dw, chan->dir, chan->id, llp.reg,
chunk->ll_region.paddr);
- #else /* CONFIG_64BIT */
+ } else {
SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
lower_32_bits(chunk->ll_region.paddr));
SET_CH_32(dw, chan->dir, chan->id, llp.msb,
upper_32_bits(chunk->ll_region.paddr));
- #endif /* CONFIG_64BIT */
+ }
}
/* Doorbell */
SET_RW_32(dw, chan->dir, doorbell,
@@ -33,6 +33,10 @@ enum dw_edma_map_format {
EDMA_MF_HDMA_COMPAT = 0x5
};
+#define DW_EDMA_CHIP_NO_MSI BIT(0)
+#define DW_EDMA_CHIP_REG32BIT BIT(1)
+#define DW_EDMA_CHIP_LOCAL_EP BIT(2)
+
/**
* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
* @dev: struct device of the eDMA controller
@@ -40,6 +44,8 @@ enum dw_edma_map_format {
* @nr_irqs: total dma irq number
* reg64bit if support 64bit write to register
* @ops DMA channel to IRQ number mapping
+ * @flags - DW_EDMA_CHIP_NO_MSI can't generate remote MSI irq
+ * - DW_EDMA_CHIP_REG32BIT only support 32bit register write
* @wr_ch_cnt DMA write channel number
* @rd_ch_cnt DMA read channel number
* @rg_region DMA register region
@@ -53,6 +59,7 @@ struct dw_edma_chip {
int id;
int nr_irqs;
const struct dw_edma_core_ops *ops;
+ u32 flags;
u16 wr_ch_cnt;
u16 rd_ch_cnt;
Allow user don't enable remote MSI irq. PCI ep probe dma locally, don't want to raise irq to remote PCI host. Add option allow force 32bit register access even at 64bit system. i.MX8 hardware only allowed 32bit register access. Add option allow EP side probe dma. remote side dma is continue physical memory, local memory is scatter list. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/dma/dw-edma/dw-edma-core.c | 7 ++++++- drivers/dma/dw-edma/dw-edma-v0-core.c | 15 +++++++++++---- include/linux/dma/edma.h | 7 +++++++ 3 files changed, 24 insertions(+), 5 deletions(-)