| Message ID | 20220422120850.769480-3-herve.codina@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RZN1 USB Host support | expand |
On Fri, 22 Apr 2022 14:08:44 +0200, Herve Codina wrote: > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one > present in the R-Car Gen2 family. > Compared to the R-Car Gen2 family, it needs three clocks instead of > one. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > --- > .../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++--- > 1 file changed, 37 insertions(+), 6 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Hervé, On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote: > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one > present in the R-Car Gen2 family. > Compared to the R-Car Gen2 family, it needs three clocks instead of > one. > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > @@ -113,6 +113,37 @@ required: > - "#size-cells" > - "#interrupt-cells" > > +if: > + properties: > + compatible: > + contains: > + enum: > + - renesas,pci-rzn1 > + > +then: > + properties: > + clocks: > + items: > + - description: Internal bus clock (AHB) for HOST > + - description: Internal bus clock (AHB) Power Management > + - description: PCI clock for USB subsystem > + clock-names: > + items: > + - const: hclk_usbh > + - const: hclk_usbpm > + - const: clk_pci_usb These are the provider names. I think they should use the consumer names: usb_hclkh, usb_hclkpm, and usb_pciclk. The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Wed, 27 Apr 2022 17:15:15 +0200 Geert Uytterhoeven <geert@linux-m68k.org> wrote: > Hi Hervé, > > On Fri, Apr 22, 2022 at 2:09 PM Herve Codina <herve.codina@bootlin.com> wrote: > > Add internal PCI bridge support for the r9a06g032 SOC. The Renesas > > RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one > > present in the R-Car Gen2 family. > > Compared to the R-Car Gen2 family, it needs three clocks instead of > > one. > > > > Signed-off-by: Herve Codina <herve.codina@bootlin.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml > > @@ -113,6 +113,37 @@ required: > > - "#size-cells" > > - "#interrupt-cells" > > > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - renesas,pci-rzn1 > > + > > +then: > > + properties: > > + clocks: > > + items: > > + - description: Internal bus clock (AHB) for HOST > > + - description: Internal bus clock (AHB) Power Management > > + - description: PCI clock for USB subsystem > > + clock-names: > > + items: > > + - const: hclk_usbh > > + - const: hclk_usbpm > > + - const: clk_pci_usb > > These are the provider names. > I think they should use the consumer names: usb_hclkh, usb_hclkpm, > and usb_pciclk. Yes, it makes sense. I will changed in v4. > > The rest looks good to me. Perfect. Thanks for the review, Hervé
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 494eb975c146..c29c46533e1b 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -32,6 +32,10 @@ properties: - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pci-r9a06g032 # RZ/N1D + - const: renesas,pci-rzn1 # RZ/N1 reg: items: @@ -41,13 +45,9 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: Device clock + clocks: true - clock-names: - items: - - const: pclk + clock-names: true resets: maxItems: 1 @@ -113,6 +113,37 @@ required: - "#size-cells" - "#interrupt-cells" +if: + properties: + compatible: + contains: + enum: + - renesas,pci-rzn1 + +then: + properties: + clocks: + items: + - description: Internal bus clock (AHB) for HOST + - description: Internal bus clock (AHB) Power Management + - description: PCI clock for USB subsystem + clock-names: + items: + - const: hclk_usbh + - const: hclk_usbpm + - const: clk_pci_usb + required: + - clock-names + +else: + properties: + clocks: + items: + - description: Device clock + clock-names: + items: + - const: pclk + unevaluatedProperties: false examples:
Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family. Compared to the R-Car Gen2 family, it needs three clocks instead of one. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++--- 1 file changed, 37 insertions(+), 6 deletions(-)