| Message ID | 20220603075908.1853011-3-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: qcom: Rework pipe_clk/pipe_clk_src handling | expand |
On Fri, Jun 03, 2022 at 10:59:05AM +0300, Dmitry Baryshkov wrote: > Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let > the clock framework automatically park the clock when the clock is > switched off and restore the parent when the clock is switched on. > > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> The Tested-by tags you added are malformed throughout the series, please review and respin (there should be two separate tags for R and T). You can drop the Tested-by tags from the two clock driver since I really tested the corresponding changes on a different platform (my fault, I replied to the cover in the last round). > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Johan
On 03/06/2022 11:17, Johan Hovold wrote: > On Fri, Jun 03, 2022 at 10:59:05AM +0300, Dmitry Baryshkov wrote: >> Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let >> the clock framework automatically park the clock when the clock is >> switched off and restore the parent when the clock is switched on. >> >> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> >> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > > The Tested-by tags you added are malformed throughout the series, please > review and respin (there should be two separate tags for R and T). Hmm, I wonder how did that happen. Probably they came from your message and I didn't notice that they were broken. > > You can drop the Tested-by tags from the two clock driver since I really > tested the corresponding changes on a different platform (my fault, I > replied to the cover in the last round). > >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, Jun 03, 2022 at 11:42:47AM +0300, Dmitry Baryshkov wrote: > On 03/06/2022 11:17, Johan Hovold wrote: > > On Fri, Jun 03, 2022 at 10:59:05AM +0300, Dmitry Baryshkov wrote: > >> Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let > >> the clock framework automatically park the clock when the clock is > >> switched off and restore the parent when the clock is switched on. > >> > >> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > >> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> > > > > The Tested-by tags you added are malformed throughout the series, please > > review and respin (there should be two separate tags for R and T). > > Hmm, I wonder how did that happen. Probably they came from your message > and I didn't notice that they were broken. You're right, I messed up when I replied to the v7 cover letter. Sorry about that and thanks for fixing it up. Johan
On 03/06/2022 11:50, Johan Hovold wrote: > On Fri, Jun 03, 2022 at 11:42:47AM +0300, Dmitry Baryshkov wrote: >> On 03/06/2022 11:17, Johan Hovold wrote: >>> On Fri, Jun 03, 2022 at 10:59:05AM +0300, Dmitry Baryshkov wrote: >>>> Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let >>>> the clock framework automatically park the clock when the clock is >>>> switched off and restore the parent when the clock is switched on. >>>> >>>> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> >>>> Tested-by: Reviewed-by: Johan Hovold <johan+linaro@kernel.org> >>> >>> The Tested-by tags you added are malformed throughout the series, please >>> review and respin (there should be two separate tags for R and T). >> >> Hmm, I wonder how did that happen. Probably they came from your message >> and I didn't notice that they were broken. > > You're right, I messed up when I replied to the v7 cover letter. Sorry > about that and thanks for fixing it up. No problem. Thanks a lot for your continuous review and testing!
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..666efa5ff978 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -17,6 +17,7 @@ #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" #include "gdsc.h" #include "reset.h" @@ -26,9 +27,7 @@ enum { P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, - P_PCIE_0_PIPE_CLK, P_PCIE_1_PHY_AUX_CLK, - P_PCIE_1_PIPE_CLK, P_SLEEP_CLK, P_UFS_PHY_RX_SYMBOL_0_CLK, P_UFS_PHY_RX_SYMBOL_1_CLK, @@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_4[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_4[] = { - { .fw_name = "pcie_0_pipe_clk", }, - { .fw_name = "bi_tcxo", }, -}; - static const struct parent_map gcc_parent_map_5[] = { { P_PCIE_1_PHY_AUX_CLK, 0 }, { P_BI_TCXO, 2 }, @@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, }; -static const struct parent_map gcc_parent_map_6[] = { - { P_PCIE_1_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_6[] = { - { .fw_name = "pcie_1_pipe_clk" }, - { .fw_name = "bi_tcxo" }, -}; - static const struct parent_map gcc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -239,17 +218,16 @@ static const struct clk_parent_data gcc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, }; @@ -269,17 +247,16 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk", + }, + .num_parents = 1, + .ops = &clk_regmap_phy_mux_ops, }, }, };