| Message ID | 20220905192310.22786-4-pali@kernel.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere, archived |
| Delegated to: | Rob Herring |
| Headers | show |
| Series | PCI: mvebu: add support for orion soc | expand |
On Mon, 05 Sep 2022 21:23:06 +0200, Pali Rohár wrote: > From: Mauri Sandberg <maukka@ext.kapsi.fi> > > Add a compatible string to bindings to indicate that orion5x PCIe is > supported too. Orion requires additional bindings for config space > registers. > > Signed-off-by: Mauri Sandberg <maukka@ext.kapsi.fi> > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > Changes in v3: > * Add more detailed information about MMIO registers > --- > Documentation/devicetree/bindings/pci/mvebu-pci.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt index 8f0bca42113f..d8d6afc6376a 100644 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt @@ -7,6 +7,7 @@ Mandatory properties: marvell,armada-xp-pcie marvell,dove-pcie marvell,kirkwood-pcie + marvell,orion5x-pcie - #address-cells, set to <3> - #size-cells, set to <2> - #interrupt-cells, set to <1> @@ -60,7 +61,8 @@ PCIe interface, having the following mandatory properties: - reg: used only for interrupt mapping, so only the first four bytes are used to refer to the correct bus number and device number. - assigned-addresses: reference to the MMIO registers used to control - this PCIe interface. + this PCIe interface. first value controls internal registers and + second value (Orion-specific) controls config space registers. - clocks: the clock associated to this PCIe interface - marvell,pcie-port: the physical PCIe port number - status: either "disabled" or "okay"