diff mbox series

[V1,8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration

Message ID 20220919143627.13803-9-vidyas@nvidia.com (mailing list archive)
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series Enhancements to pcie-tegra194 driver | expand

Commit Message

Vidya Sagar Sept. 19, 2022, 2:36 p.m. UTC
Set ENABLE_L2_EXIT_RATE_CHANGE to request UPHY PLL rate change to Gen1
during initialization. This helps in the below surprise down cases,
  - Surprise down happens at Gen3/Gen4 link speed
  - Surprise down happens and external REFCLK is cut off which causes
UPHY PLL rate to deviate to an invalid rate

ENABLE_L2_EXIT_RATE_CHANGE needs to be set to bring the UPHY PLL rate
back to Gen1 during controller initialization for the link up.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

kernel test robot Sept. 19, 2022, 4:33 p.m. UTC | #1
Hi Vidya,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on helgaas-pci/next]
[also build test WARNING on tegra/for-next linus/master v6.0-rc6 next-20220919]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Vidya-Sagar/Enhancements-to-pcie-tegra194-driver/20220919-224101
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20220920/202209200038.mZZFPD7g-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/3b12c1aea8ddaae70567a332fc676c76076bf624
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Vidya-Sagar/Enhancements-to-pcie-tegra194-driver/20220919-224101
        git checkout 3b12c1aea8ddaae70567a332fc676c76076bf624
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/phy/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/phy/tegra/phy-tegra194-p2u.c:89:5: warning: no previous prototype for 'tegra_p2u_calibrate' [-Wmissing-prototypes]
      89 | int tegra_p2u_calibrate(struct phy *x)
         |     ^~~~~~~~~~~~~~~~~~~


vim +/tegra_p2u_calibrate +89 drivers/phy/tegra/phy-tegra194-p2u.c

    88	
  > 89	int tegra_p2u_calibrate(struct phy *x)
    90	{
    91		struct tegra_p2u *phy = phy_get_drvdata(x);
    92		u32 val;
    93	
    94		val = p2u_readl(phy, P2U_CONTROL_CMN);
    95		val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
    96		p2u_writel(phy, val, P2U_CONTROL_CMN);
    97	
    98		return 0;
    99	}
   100
Vinod Koul Sept. 20, 2022, 6:11 a.m. UTC | #2
On 19-09-22, 20:06, Vidya Sagar wrote:
> Set ENABLE_L2_EXIT_RATE_CHANGE to request UPHY PLL rate change to Gen1
> during initialization. This helps in the below surprise down cases,
>   - Surprise down happens at Gen3/Gen4 link speed
>   - Surprise down happens and external REFCLK is cut off which causes
> UPHY PLL rate to deviate to an invalid rate
> 
> ENABLE_L2_EXIT_RATE_CHANGE needs to be set to bring the UPHY PLL rate
> back to Gen1 during controller initialization for the link up.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
> index 1415ca71de38..fb710e89acac 100644
> --- a/drivers/phy/tegra/phy-tegra194-p2u.c
> +++ b/drivers/phy/tegra/phy-tegra194-p2u.c
> @@ -15,6 +15,7 @@
>  #include <linux/phy/phy.h>
>  
>  #define P2U_CONTROL_CMN			0x74
> +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE		BIT(13)
>  #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN			BIT(20)
>  
>  #define P2U_PERIODIC_EQ_CTRL_GEN3	0xc0
> @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x)
>  	return 0;
>  }
>  
> +int tegra_p2u_calibrate(struct phy *x)

why not static?

> +{
> +	struct tegra_p2u *phy = phy_get_drvdata(x);
> +	u32 val;
> +
> +	val = p2u_readl(phy, P2U_CONTROL_CMN);
> +	val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
> +	p2u_writel(phy, val, P2U_CONTROL_CMN);
> +
> +	return 0;
> +}
> +
>  static const struct phy_ops ops = {
>  	.power_on = tegra_p2u_power_on,
> +	.calibrate = tegra_p2u_calibrate,
>  	.owner = THIS_MODULE,
>  };
>  
> -- 
> 2.17.1
diff mbox series

Patch

diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 1415ca71de38..fb710e89acac 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -15,6 +15,7 @@ 
 #include <linux/phy/phy.h>
 
 #define P2U_CONTROL_CMN			0x74
+#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE		BIT(13)
 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN			BIT(20)
 
 #define P2U_PERIODIC_EQ_CTRL_GEN3	0xc0
@@ -85,8 +86,21 @@  static int tegra_p2u_power_on(struct phy *x)
 	return 0;
 }
 
+int tegra_p2u_calibrate(struct phy *x)
+{
+	struct tegra_p2u *phy = phy_get_drvdata(x);
+	u32 val;
+
+	val = p2u_readl(phy, P2U_CONTROL_CMN);
+	val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE;
+	p2u_writel(phy, val, P2U_CONTROL_CMN);
+
+	return 0;
+}
+
 static const struct phy_ops ops = {
 	.power_on = tegra_p2u_power_on,
+	.calibrate = tegra_p2u_calibrate,
 	.owner = THIS_MODULE,
 };