diff mbox series

[v6,06/10] PCI: dwc: Add reset_all_bars flag

Message ID 20220922080647.3489791-7-yoshihiro.shimoda.uh@renesas.com (mailing list archive)
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series PCI: rcar-gen4: Add R-Car Gen4 PCIe support | expand

Commit Message

Yoshihiro Shimoda Sept. 22, 2022, 8:06 a.m. UTC
Some PCIe endpoint drivers reset all BARs in each ep_init() ops.
So, we can reset the BARs into the common code if the flag is set.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
 drivers/pci/controller/dwc/pcie-designware.h    |  1 +
 2 files changed, 11 insertions(+)

Comments

Lorenzo Pieralisi Nov. 11, 2022, 12:34 p.m. UTC | #1
On Thu, Sep 22, 2022 at 05:06:43PM +0900, Yoshihiro Shimoda wrote:
> Some PCIe endpoint drivers reset all BARs in each ep_init() ops.
> So, we can reset the BARs into the common code if the flag is set.

Is there a reason why only some drivers do it ? What I am really asking
is whether instead of a flag we could reset them unconditionally in all
drivers.

It would be good to come up with a set of guidelines on kernel
expectations rather than adding them per EP.

Lorenzo

> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
>  drivers/pci/controller/dwc/pcie-designware.h    |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 1b7e9e1b8d52..a79482824e74 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -83,6 +83,14 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
>  }
>  EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
>  
> +static void dw_pcie_ep_reset_all_bars(struct dw_pcie *pci)
> +{
> +	enum pci_barno bar;
> +
> +	for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++)
> +		dw_pcie_ep_reset_bar(pci, bar);
> +}
> +
>  static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
>  		u8 cap_ptr, u8 cap)
>  {
> @@ -759,6 +767,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  
>  	if (ep->ops->ep_init)
>  		ep->ops->ep_init(ep);
> +	if (ep->reset_all_bars)
> +		dw_pcie_ep_reset_all_bars(pci);
>  
>  	ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
>  			       ep->page_size);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 9ed9621a12e4..0ad9ed77affb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -353,6 +353,7 @@ struct dw_pcie_ep {
>  	void __iomem		*msi_mem;
>  	phys_addr_t		msi_mem_phys;
>  	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];
> +	bool			reset_all_bars;
>  };
>  
>  struct dw_pcie_ops {
> -- 
> 2.25.1
>
Yoshihiro Shimoda Nov. 14, 2022, 6:18 a.m. UTC | #2
Hi Lorenzo,

> From: Lorenzo Pieralisi, Sent: Friday, November 11, 2022 9:34 PM
> 
> On Thu, Sep 22, 2022 at 05:06:43PM +0900, Yoshihiro Shimoda wrote:
> > Some PCIe endpoint drivers reset all BARs in each ep_init() ops.
> > So, we can reset the BARs into the common code if the flag is set.
> 
> Is there a reason why only some drivers do it ? What I am really asking
> is whether instead of a flag we could reset them unconditionally in all
> drivers.
> 
> It would be good to come up with a set of guidelines on kernel
> expectations rather than adding them per EP.

Thank you very much for your comments! I realized that this is
completely unnecessary code because a PCIe endpoint function driver
will call pci_epc_set_bar() to prepare BAR(s). So, I'll drop this patch
on v7.

Best regards,
Yoshihiro Shimoda

> Lorenzo
> 
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
> >  drivers/pci/controller/dwc/pcie-designware.h    |  1 +
> >  2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 1b7e9e1b8d52..a79482824e74 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -83,6 +83,14 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> >  }
> >  EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
> >
> > +static void dw_pcie_ep_reset_all_bars(struct dw_pcie *pci)
> > +{
> > +	enum pci_barno bar;
> > +
> > +	for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++)
> > +		dw_pcie_ep_reset_bar(pci, bar);
> > +}
> > +
> >  static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
> >  		u8 cap_ptr, u8 cap)
> >  {
> > @@ -759,6 +767,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> >
> >  	if (ep->ops->ep_init)
> >  		ep->ops->ep_init(ep);
> > +	if (ep->reset_all_bars)
> > +		dw_pcie_ep_reset_all_bars(pci);
> >
> >  	ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
> >  			       ep->page_size);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 9ed9621a12e4..0ad9ed77affb 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -353,6 +353,7 @@ struct dw_pcie_ep {
> >  	void __iomem		*msi_mem;
> >  	phys_addr_t		msi_mem_phys;
> >  	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];
> > +	bool			reset_all_bars;
> >  };
> >
> >  struct dw_pcie_ops {
> > --
> > 2.25.1
> >
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1b7e9e1b8d52..a79482824e74 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -83,6 +83,14 @@  void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
 
+static void dw_pcie_ep_reset_all_bars(struct dw_pcie *pci)
+{
+	enum pci_barno bar;
+
+	for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++)
+		dw_pcie_ep_reset_bar(pci, bar);
+}
+
 static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
 		u8 cap_ptr, u8 cap)
 {
@@ -759,6 +767,8 @@  int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 
 	if (ep->ops->ep_init)
 		ep->ops->ep_init(ep);
+	if (ep->reset_all_bars)
+		dw_pcie_ep_reset_all_bars(pci);
 
 	ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
 			       ep->page_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9ed9621a12e4..0ad9ed77affb 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -353,6 +353,7 @@  struct dw_pcie_ep {
 	void __iomem		*msi_mem;
 	phys_addr_t		msi_mem_phys;
 	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];
+	bool			reset_all_bars;
 };
 
 struct dw_pcie_ops {