| Message ID | 20230404052714.51315-2-mika.westerberg@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI/PM: Resume/reset wait time change | expand |
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 57ddcc59af30..6b5b2a818e65 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -572,7 +572,8 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev) static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev) { - pci_bridge_wait_for_secondary_bus(pci_dev, "resume", PCI_RESET_WAIT); + pci_bridge_wait_for_secondary_bus(pci_dev, "resume", + PCIE_RESET_READY_POLL_MS); /* * When powering on a bridge from D3cold, the whole hierarchy may be * powered on into D0uninitialized state, resume them to give them a
The PCIe spec prescribes that a device may take up to 1 second to recover from reset and this same delay is prescribed when coming out of D3cold (as that involves reset too). The device may extend this 1 second delay through Request Retry Status completions and we accommondate for that in Linux with 60 second cap, only in reset code path, not in resume code path. However, a device has surfaced, namely Intel Titan Ridge xHCI, which requires longer delay also in the resume code path. For this reason make the resume code path to use this same extended delay than with the reset path. Reported-by: Chris Chiu <chris.chiu@canonical.com> Link: https://bugzilla.kernel.org/show_bug.cgi?id=216728 Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> --- drivers/pci/pci-driver.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)