| Message ID | 20230719155707.1948698-2-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | [v3,1/2] PCI: layerscape: Add support for Link down notification | expand |
On Wed, Jul 19, 2023 at 11:57:07AM -0400, Frank Li wrote: > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > A workaround for the issue where the PCI Express Endpoint (EP) controller > loses the values of the Maximum Link Width and Supported Link Speed from > the Link Capabilities Register, which initially configured by the Reset > Configuration Word (RCW) during a link-down or hot reset event. > > Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") > Acked-by: Manivannan Sadhasivam <mani@kernel.org> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > change from v2 to v3 > - fix subject typo capabilities > change from v1 to v2: > - add comments at restore register > - add fixes tag > - dw_pcie_writew_dbi to dw_pcie_writel_dbi > > .../pci/controller/dwc/pci-layerscape-ep.c | 21 ++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index e0969ff2ddf7..39dbd911c3f8 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -45,6 +45,7 @@ struct ls_pcie_ep { > struct pci_epc_features *ls_epc; > const struct ls_pcie_ep_drvdata *drvdata; > int irq; > + u32 lnkcap; > bool big_endian; > }; > > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > struct ls_pcie_ep *pcie = dev_id; > struct dw_pcie *pci = pcie->pci; > u32 val, cfg; > + u8 offset; > > val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); > ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); > @@ -81,12 +83,25 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > return IRQ_NONE; > > if (val & PEX_PF0_PME_MES_DR_LUD) { > + > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + > + /* > + * The values of the Maximum Link Width and Supported Link > + * Speed from the Link Capabilities Register will be lost > + * during link down or hot reset. Restore initial value > + * that configured by the Reset Configuration Word (RCW). > + */ > + dw_pcie_dbi_ro_wr_en(pci); > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); > + dw_pcie_dbi_ro_wr_dis(pci); > + > cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); > cfg |= PEX_PF0_CFG_READY; > ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); > dw_pcie_ep_linkup(&pci->ep); > > - dev_dbg(pci->dev, "Link up\n"); > + dev_err(pci->dev, "Link up\n"); Sorry, Just found that. mistake merge a debug code. It should be dev_dbg here, will send update patch soon Frank > } else if (val & PEX_PF0_PME_MES_DR_LDD) { > dev_dbg(pci->dev, "Link down\n"); > pci_epc_linkdown(pci->ep.epc); > @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > struct ls_pcie_ep *pcie; > struct pci_epc_features *ls_epc; > struct resource *dbi_base; > + u8 offset; > int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, pcie); > > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > + > ret = dw_pcie_ep_init(&pci->ep); > if (ret) > return ret; > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index e0969ff2ddf7..39dbd911c3f8 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,6 +45,7 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; + u32 lnkcap; bool big_endian; }; @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; + u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -81,12 +83,25 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + /* + * The values of the Maximum Link Width and Supported Link + * Speed from the Link Capabilities Register will be lost + * during link down or hot reset. Restore initial value + * that configured by the Reset Configuration Word (RCW). + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); dw_pcie_ep_linkup(&pci->ep); - dev_dbg(pci->dev, "Link up\n"); + dev_err(pci->dev, "Link up\n"); } else if (val & PEX_PF0_PME_MES_DR_LDD) { dev_dbg(pci->dev, "Link down\n"); pci_epc_linkdown(pci->ep.epc); @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret;