| Message ID | 20230721214740.256602-4-Smita.KoralahalliChannabasappa@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap | expand |
On 7/21/23 2:47 PM, Smita Koralahalli wrote: > Reuse pcie_aer_is_native() to determine the native AER ownership. Although it is straightforward, IMO, the commit log should include few words about *why* you are making this change. For example, usage of host_bride->native_aer does not cover command line override of AER ownership. So use pcie_aer_is_native() to determine the ownership. With that fixed, Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> > --- > v2: > Replaced pcie_aer_is_native() at a later stage for automated > backports. > --- > drivers/cxl/pci.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 2323169b6e5f..44a21ab7add5 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > void __iomem *addr; > u32 orig_val, val, mask; > @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) > } > > /* BIOS has PCIe AER error control */ > - if (!host_bridge->native_aer) > + if (!pcie_aer_is_native(pdev)) > return 0; > > rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
On 21.07.23 21:47:40, Smita Koralahalli wrote: > Reuse pcie_aer_is_native() to determine the native AER ownership. > > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> With Sathyanarayanan comments addressed: Reviewed-by: Robert Richter <rrichter@amd.com> > --- > v2: > Replaced pcie_aer_is_native() at a later stage for automated > backports. > --- > drivers/cxl/pci.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 2323169b6e5f..44a21ab7add5 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > void __iomem *addr; > u32 orig_val, val, mask; > @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) > } > > /* BIOS has PCIe AER error control */ > - if (!host_bridge->native_aer) > + if (!pcie_aer_is_native(pdev)) > return 0; > > rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); > -- > 2.17.1 >
Smita Koralahalli wrote:
> Reuse pcie_aer_is_native() to determine the native AER ownership.
Looks good.
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 2323169b6e5f..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) } /* BIOS has PCIe AER error control */ - if (!host_bridge->native_aer) + if (!pcie_aer_is_native(pdev)) return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
Reuse pcie_aer_is_native() to determine the native AER ownership. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- v2: Replaced pcie_aer_is_native() at a later stage for automated backports. --- drivers/cxl/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)