| Message ID | 20230802155748.212377-1-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | [v7,1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions | expand |
On Wed, Aug 02, 2023 at 11:57:47AM -0400, Frank Li wrote: > Introduce helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE. s/dw_pcie_get_ltssm/dw_pcie_get_ltssm()/ > Add callback .pme_turn_off and .exit_from_l2 for platform specific PME > handling. > > Add common dw_pcie_suspend(resume)_noirq() API to avoid duplicated code > in dwc pci host controller platform driver. > > Typical L2 entry workflow/dw_pcie_suspend_noirq() > > 1. Transmit PME turn off signal to PCI devices and wait for PME_To_Ack. > 2. Await link entering L2_IDLE state. > > Typical L2 exit workflow/dw_pcie_resume_noirq() > > 1. Issue exit from L2 command. > 2. Reinitialize PCI host. > 3. Wait for link to become active. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > Change from v6 to v7 > - change according to Manivannan's comments. > fix sleep value 100 (should be 1000 for 1ms). > + * PCI Express Base Specification Rev 4.0 Section 5.3.3.2.1 PME > + * Synchronization Recommends 1ms to 10ms timeout to check L2 ready. > + */ > + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, > + 1000, 10000, false, pci); Thanks for the spec citation. Can you please reference the current spec, i.e., "PCIe r6.0, sec 5.3.3.2.1". s/Recommends/recommends/ It would really be great to have a #define for this since the bare numbers are not very meaningful and they're not specific to DWC so a #define would let us find similar situations in other drivers. Bjorn
On Wed, Aug 02, 2023 at 11:31:38AM -0500, Bjorn Helgaas wrote: > On Wed, Aug 02, 2023 at 11:57:47AM -0400, Frank Li wrote: > > Introduce helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE. > > s/dw_pcie_get_ltssm/dw_pcie_get_ltssm()/ > > > Add callback .pme_turn_off and .exit_from_l2 for platform specific PME > > handling. > > > > Add common dw_pcie_suspend(resume)_noirq() API to avoid duplicated code > > in dwc pci host controller platform driver. > > > > Typical L2 entry workflow/dw_pcie_suspend_noirq() > > > > 1. Transmit PME turn off signal to PCI devices and wait for PME_To_Ack. > > 2. Await link entering L2_IDLE state. > > > > Typical L2 exit workflow/dw_pcie_resume_noirq() > > > > 1. Issue exit from L2 command. > > 2. Reinitialize PCI host. > > 3. Wait for link to become active. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > Change from v6 to v7 > > - change according to Manivannan's comments. > > fix sleep value 100 (should be 1000 for 1ms). > > > + * PCI Express Base Specification Rev 4.0 Section 5.3.3.2.1 PME > > + * Synchronization Recommends 1ms to 10ms timeout to check L2 ready. > > + */ > > + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, > > + 1000, 10000, false, pci); > > Thanks for the spec citation. Can you please reference the current > spec, i.e., "PCIe r6.0, sec 5.3.3.2.1". > > s/Recommends/recommends/ > > It would really be great to have a #define for this since the bare > numbers are not very meaningful and they're not specific to DWC so a > #define would let us find similar situations in other drivers. how about define as #define PCI_PME_TO_L2_TIMEOUT 10000 ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, PCI_PME_TO_L2_TIMEOUT/10, PCI_PME_TO_L2_TIMEOUT, false, pci); where is good place PCI_PME_TO_L2_TIMEOUT in? pcie-designware.h or pci.h? Frank > > Bjorn
On Wed, Aug 02, 2023 at 02:44:52PM -0400, Frank Li wrote: > On Wed, Aug 02, 2023 at 11:31:38AM -0500, Bjorn Helgaas wrote: > > On Wed, Aug 02, 2023 at 11:57:47AM -0400, Frank Li wrote: > > > Introduce helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE. > > > Add callback .pme_turn_off and .exit_from_l2 for platform specific PME > > > handling. > > > + * PCI Express Base Specification Rev 4.0 Section 5.3.3.2.1 PME > > > + * Synchronization Recommends 1ms to 10ms timeout to check L2 ready. > > > + */ > > > + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, > > > + 1000, 10000, false, pci); > > It would really be great to have a #define for this since the bare > > numbers are not very meaningful and they're not specific to DWC so a > > #define would let us find similar situations in other drivers. > > how about define as > > #define PCI_PME_TO_L2_TIMEOUT 10000 > > ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, > PCI_PME_TO_L2_TIMEOUT/10, PCI_PME_TO_L2_TIMEOUT, false, pci); > > where is good place PCI_PME_TO_L2_TIMEOUT in? > > pcie-designware.h or pci.h? I think drivers/pci/pci.h since it's only useful inside drivers/pci, and it's not specific to dwc. Maybe "PCIE_" (not "PCI_") since this is a PCIe-specific thing. You could put it next to PCIE_LINK_RETRAIN_TIMEOUT_MS and add a "_US" suffix so we know what the units are. Bjorn
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9952057c8819c..bc01ecc1c3ec8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -8,6 +8,7 @@ * Author: Jingoo Han <jg1.han@samsung.com> */ +#include <linux/iopoll.h> #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/msi.h> @@ -807,3 +808,80 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); + +int dw_pcie_suspend_noirq(struct dw_pcie *pci) +{ + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + int ret; + + /* + * If L1SS is supported, then do not put the link into L2 as some + * devices such as NVMe expect low resume latency. + */ + if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) + return 0; + + if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) + return 0; + + if (!pci->pp.ops->pme_turn_off) + return 0; + + pci->pp.ops->pme_turn_off(&pci->pp); + + /* + * PCI Express Base Specification Rev 4.0 Section 5.3.3.2.1 PME + * Synchronization Recommends 1ms to 10ms timeout to check L2 ready. + */ + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, + 1000, 10000, false, pci); + if (ret) { + dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); + return ret; + } + + if (pci->pp.ops->host_deinit) + pci->pp.ops->host_deinit(&pci->pp); + + pci->suspended = true; + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); + +int dw_pcie_resume_noirq(struct dw_pcie *pci) +{ + int ret; + + if (!pci->suspended) + return 0; + + pci->suspended = false; + + if (!pci->pp.ops->exit_from_l2) + return 0; + + pci->pp.ops->exit_from_l2(&pci->pp); + + if (pci->pp.ops->host_init) { + ret = pci->pp.ops->host_init(&pci->pp); + if (ret) { + dev_err(pci->dev, "Host init failed! ret = %d\n", ret); + return ret; + } + } + + dw_pcie_setup_rc(&pci->pp); + + ret = dw_pcie_start_link(pci); + if (ret) + return ret; + + ret = dw_pcie_wait_for_link(pci); + if (ret) + return ret; + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 79713ce075cc1..cbba3ed19b3c0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -288,10 +288,21 @@ enum dw_pcie_core_rst { DW_PCIE_NUM_CORE_RSTS }; +enum dw_pcie_ltssm { + DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, + /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */ + DW_PCIE_LTSSM_DETECT_QUIET = 0x0, + DW_PCIE_LTSSM_DETECT_ACT = 0x1, + DW_PCIE_LTSSM_L0 = 0x11, + DW_PCIE_LTSSM_L2_IDLE = 0x15, +}; + struct dw_pcie_host_ops { int (*host_init)(struct dw_pcie_rp *pp); void (*host_deinit)(struct dw_pcie_rp *pp); int (*msi_host_init)(struct dw_pcie_rp *pp); + void (*pme_turn_off)(struct dw_pcie_rp *pp); + void (*exit_from_l2)(struct dw_pcie_rp *pp); }; struct dw_pcie_rp { @@ -364,6 +375,7 @@ struct dw_pcie_ops { void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); + enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); }; @@ -393,6 +405,7 @@ struct dw_pcie { struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; + bool suspended; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -430,6 +443,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); void dw_pcie_edma_remove(struct dw_pcie *pci); +int dw_pcie_suspend_noirq(struct dw_pcie *pci); +int dw_pcie_resume_noirq(struct dw_pcie *pci); + static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { dw_pcie_write_dbi(pci, reg, 0x4, val); @@ -501,6 +517,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) pci->ops->stop_link(pci); } +static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) +{ + u32 val; + + if (pci->ops && pci->ops->get_ltssm) + return pci->ops->get_ltssm(pci); + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); + + return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val); +} + #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
Introduce helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE. Add callback .pme_turn_off and .exit_from_l2 for platform specific PME handling. Add common dw_pcie_suspend(resume)_noirq() API to avoid duplicated code in dwc pci host controller platform driver. Typical L2 entry workflow/dw_pcie_suspend_noirq() 1. Transmit PME turn off signal to PCI devices and wait for PME_To_Ack. 2. Await link entering L2_IDLE state. Typical L2 exit workflow/dw_pcie_resume_noirq() 1. Issue exit from L2 command. 2. Reinitialize PCI host. 3. Wait for link to become active. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Change from v6 to v7 - change according to Manivannan's comments. fix sleep value 100 (should be 1000 for 1ms). use dev_err when timeout Change from v5 to v6: - refine commit message change according to Manivannan's comments. - remove reduncate step dw_pcie_set_dstate() - return 0 when .pme_turn_off is zero - call host_deinit() in suspend - check .host_deinit and .host_init point before call. Change from v4 to v5: - Closes: https://lore.kernel.org/oe-kbuild-all/202307211904.zExw4Q8H-lkp@intel.com/ Change from v3 to v4: - change according to Manivannan's comments. I hope I have not missed anything. quite long discuss thread Change from v2 to v3: - Basic rewrite whole patch according rob herry suggestion. put common function into dwc, so more soc can share the same logic. .../pci/controller/dwc/pcie-designware-host.c | 78 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 28 +++++++ 2 files changed, 106 insertions(+)