| Message ID | 20230929115723.7864-2-ilpo.jarvinen@linux.intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | Add PCIe Bandwidth Controller | expand |
On Fri, Sep 29, 2023 at 02:57:14PM +0300, Ilpo Järvinen wrote: > PCIe Bandwidth Controller performs RMW accesses the Link Control 2 ^ to > Register which can occur concurrently to other sources of Link Control > 2 Register writes. Therefore, add Link Control 2 Register among the PCI > Express Capability Registers that need RMW locking. [...] > --- a/Documentation/PCI/pciebus-howto.rst > +++ b/Documentation/PCI/pciebus-howto.rst > @@ -218,7 +218,7 @@ that is shared between many drivers including the service drivers. > RMW Capability accessors (pcie_capability_clear_and_set_word(), > pcie_capability_set_word(), and pcie_capability_clear_word()) protect > a selected set of PCI Express Capability Registers (Link Control > -Register and Root Control Register). Any change to those registers > -should be performed using RMW accessors to avoid problems due to > -concurrent updates. For the up-to-date list of protected registers, > -see pcie_capability_clear_and_set_word(). > +Register, Root Control Register, and Link Control 2 Register). Any > +change to those registers should be performed using RMW accessors to > +avoid problems due to concurrent updates. For the up-to-date list of > +protected registers, see pcie_capability_clear_and_set_word(). Maybe use a list of bullet points of the affected registers so that this can be extended more easily in the future. Otherwise, Reviewed-by: Lukas Wunner <lukas@wunner.de>
diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst index a0027e8fb0d0..3ba322ca1ce1 100644 --- a/Documentation/PCI/pciebus-howto.rst +++ b/Documentation/PCI/pciebus-howto.rst @@ -218,7 +218,7 @@ that is shared between many drivers including the service drivers. RMW Capability accessors (pcie_capability_clear_and_set_word(), pcie_capability_set_word(), and pcie_capability_clear_word()) protect a selected set of PCI Express Capability Registers (Link Control -Register and Root Control Register). Any change to those registers -should be performed using RMW accessors to avoid problems due to -concurrent updates. For the up-to-date list of protected registers, -see pcie_capability_clear_and_set_word(). +Register, Root Control Register, and Link Control 2 Register). Any +change to those registers should be performed using RMW accessors to +avoid problems due to concurrent updates. For the up-to-date list of +protected registers, see pcie_capability_clear_and_set_word(). diff --git a/include/linux/pci.h b/include/linux/pci.h index 8c7c2c3c6c65..16db80f8b15c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1243,6 +1243,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, { switch (pos) { case PCI_EXP_LNKCTL: + case PCI_EXP_LNKCTL2: case PCI_EXP_RTCTL: return pcie_capability_clear_and_set_word_locked(dev, pos, clear, set);
PCIe Bandwidth Controller performs RMW accesses the Link Control 2 Register which can occur concurrently to other sources of Link Control 2 Register writes. Therefore, add Link Control 2 Register among the PCI Express Capability Registers that need RMW locking. Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> --- Documentation/PCI/pciebus-howto.rst | 8 ++++---- include/linux/pci.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-)