| Message ID | 20231227182727.1747435-17-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: imx6: Clean up and add imx95 pci support | expand |
On Wed, Dec 27, 2023 at 01:27:27PM -0500, Frank Li wrote: Subject: PCI: imx6: Add iMX95 Endpoint (EP) support > Add iMX95 EP function support and add 64bit address support. Internal bus Remove 'function' as that refers to endpoint function. > bridge for PCI support 64bit dma address in iMX95. So set call > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). > 'Hence, call dma_set_mask_and_coherent() to set 64 bit DMA mask.' > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Change from v3 to v4 > - change align to 4k for imx95 > Change from v1 to v3 > - new patches at v3 > > drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 6a58fd63a9dd2..00ec59867c17b 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -75,6 +75,7 @@ enum imx6_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX95_EP, > }; > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > @@ -84,6 +85,7 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) > #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) > +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > break; > case IMX7D: > case IMX95: > + case IMX95_EP: > break; > case IMX8MM: > case IMX8MM_EP: > @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +/* > + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > + * ================================================================================================ > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit I couldn't understand above. And not aligned properly. > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > + * BAR4 | Enable | 32-bit | 1M | Programmable Size > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > + */ > +static const struct pci_epc_features imx95_pcie_epc_features = { > + .msi_capable = true, > + .bar_fixed_size[1] = SZ_64K, > + .align = SZ_4K, > +}; > + > static const struct pci_epc_features* > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) > { > @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; > > + /* Use FIXME here. - Mani > + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from > + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed > + * after all dts added "dbi2" reg. > + */ > + if (imx6_pcie->drvdata->variant == IMX95_EP) > + pci->dbi_base2 = NULL; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) > "unable to find iomuxc registers\n"); > } > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > + > /* Grab PCIe PHY Tx Settings */ > if (of_property_read_u32(node, "fsl,tx-deemph-gen1", > &imx6_pcie->tx_deemph_gen1)) > @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .epc_features = &imx8m_pcie_epc_features, > }, > + [IMX95_EP] = { > + .variant = IMX95_EP, > + .flags = IMX6_PCIE_FLAG_HAS_SERDES | > + IMX6_PCIE_FLAG_SUPPORT_64BIT, > + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, > + .ltssm_off = IMX95_PE0_GEN_CTRL_3, > + .ltssm_mask = IMX95_PCIE_LTSSM_EN, > + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > + .init_phy = imx95_pcie_init_phy, > + .epc_features = &imx95_pcie_epc_features, > + .mode = DW_PCIE_EP_TYPE, > + }, > }; > > static const struct of_device_id imx6_pcie_of_match[] = { > @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 >
On Sun, Jan 07, 2024 at 11:56:54AM +0530, Manivannan Sadhasivam wrote: > On Wed, Dec 27, 2023 at 01:27:27PM -0500, Frank Li wrote: > > Subject: PCI: imx6: Add iMX95 Endpoint (EP) support > > > Add iMX95 EP function support and add 64bit address support. Internal bus > > Remove 'function' as that refers to endpoint function. > > > bridge for PCI support 64bit dma address in iMX95. So set call > > dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). > > > > 'Hence, call dma_set_mask_and_coherent() to set 64 bit DMA mask.' > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > > > Notes: > > Change from v3 to v4 > > - change align to 4k for imx95 > > Change from v1 to v3 > > - new patches at v3 > > > > drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > > index 6a58fd63a9dd2..00ec59867c17b 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -75,6 +75,7 @@ enum imx6_pcie_variants { > > IMX8MQ_EP, > > IMX8MM_EP, > > IMX8MP_EP, > > + IMX95_EP, > > }; > > > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > > @@ -84,6 +85,7 @@ enum imx6_pcie_variants { > > #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) > > #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) > > #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) > > +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > > > #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > > > @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > > break; > > case IMX7D: > > case IMX95: > > + case IMX95_EP: > > break; > > case IMX8MM: > > case IMX8MM_EP: > > @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > > .align = SZ_64K, > > }; > > > > +/* > > + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > > + * ================================================================================================ > > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > > + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit > > I couldn't understand above. And not aligned properly. If BAR0 is 64bit, BAR1 will be disable. (Supposed it is default). If BAR0 is 32bit, BAR1 will 64KB fixed sized. Aligned because 'tab' show problem in patch. It show algin at '|" at code. Frank > > > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > > + * BAR4 | Enable | 32-bit | 1M | Programmable Size > > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > > + */ > > +static const struct pci_epc_features imx95_pcie_epc_features = { > > + .msi_capable = true, > > + .bar_fixed_size[1] = SZ_64K, > > + .align = SZ_4K, > > +}; > > + > > static const struct pci_epc_features* > > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) > > { > > @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > > > pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; > > > > + /* > > Use FIXME here. > > - Mani > > > + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from > > + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed > > + * after all dts added "dbi2" reg. > > + */ > > + if (imx6_pcie->drvdata->variant == IMX95_EP) > > + pci->dbi_base2 = NULL; > > + > > ret = dw_pcie_ep_init(ep); > > if (ret) { > > dev_err(dev, "failed to initialize endpoint\n"); > > @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) > > "unable to find iomuxc registers\n"); > > } > > > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > > + > > /* Grab PCIe PHY Tx Settings */ > > if (of_property_read_u32(node, "fsl,tx-deemph-gen1", > > &imx6_pcie->tx_deemph_gen1)) > > @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { > > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > > .epc_features = &imx8m_pcie_epc_features, > > }, > > + [IMX95_EP] = { > > + .variant = IMX95_EP, > > + .flags = IMX6_PCIE_FLAG_HAS_SERDES | > > + IMX6_PCIE_FLAG_SUPPORT_64BIT, > > + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, > > + .ltssm_off = IMX95_PE0_GEN_CTRL_3, > > + .ltssm_mask = IMX95_PCIE_LTSSM_EN, > > + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > > + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > > + .init_phy = imx95_pcie_init_phy, > > + .epc_features = &imx95_pcie_epc_features, > > + .mode = DW_PCIE_EP_TYPE, > > + }, > > }; > > > > static const struct of_device_id imx6_pcie_of_match[] = { > > @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { > > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > > + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > > {}, > > }; > > > > -- > > 2.34.1 > > > > -- > மணிவண்ணன் சதாசிவம்
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 6a58fd63a9dd2..00ec59867c17b 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -75,6 +75,7 @@ enum imx6_pcie_variants { IMX8MQ_EP, IMX8MM_EP, IMX8MP_EP, + IMX95_EP, }; #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) @@ -84,6 +85,7 @@ enum imx6_pcie_variants { #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) @@ -620,6 +622,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) break; case IMX7D: case IMX95: + case IMX95_EP: break; case IMX8MM: case IMX8MM_EP: @@ -1063,6 +1066,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { .align = SZ_64K, }; +/* + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme + * ================================================================================================ + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size + * | (BAR0 is 64-bit) | if BAR0 is 32-bit | | As Bar0 is 64bit + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size + * BAR4 | Enable | 32-bit | 1M | Programmable Size + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size + */ +static const struct pci_epc_features imx95_pcie_epc_features = { + .msi_capable = true, + .bar_fixed_size[1] = SZ_64K, + .align = SZ_4K, +}; + static const struct pci_epc_features* imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -1105,6 +1125,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; + /* + * db2 information should fetch from dtb file. dw_pcie_ep_init() can get dbi_base2 from + * "dbi2" if pci->dbi_base2 is NULL. All code related pcie_dbi2_offset should be removed + * after all dts added "dbi2" reg. + */ + if (imx6_pcie->drvdata->variant == IMX95_EP) + pci->dbi_base2 = NULL; + ret = dw_pcie_ep_init(ep); if (ret) { dev_err(dev, "failed to initialize endpoint\n"); @@ -1355,6 +1383,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) "unable to find iomuxc registers\n"); } + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", &imx6_pcie->tx_deemph_gen1)) @@ -1557,6 +1588,19 @@ static const struct imx6_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, }, + [IMX95_EP] = { + .variant = IMX95_EP, + .flags = IMX6_PCIE_FLAG_HAS_SERDES | + IMX6_PCIE_FLAG_SUPPORT_64BIT, + .clk_names = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}, + .ltssm_off = IMX95_PE0_GEN_CTRL_3, + .ltssm_mask = IMX95_PCIE_LTSSM_EN, + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, + .init_phy = imx95_pcie_init_phy, + .epc_features = &imx95_pcie_epc_features, + .mode = DW_PCIE_EP_TYPE, + }, }; static const struct of_device_id imx6_pcie_of_match[] = { @@ -1571,6 +1615,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, {}, };
Add iMX95 EP function support and add 64bit address support. Internal bus bridge for PCI support 64bit dma address in iMX95. So set call dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)). Signed-off-by: Frank Li <Frank.Li@nxp.com> --- Notes: Change from v3 to v4 - change align to 4k for imx95 Change from v1 to v3 - new patches at v3 drivers/pci/controller/dwc/pci-imx6.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)