| Message ID | 20240102-j7200-pcie-s2r-v5-9-4b8c46711ded@bootlin.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add suspend to ram support for PCIe on J7200 | expand |
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed1846847..c47b1d3b5887 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -16,6 +16,9 @@ /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ #define PCIE_T_PVPERL_MS 100 +/* REFCLK stable before PERST# inactive from PCIe card Electromechanical Spec */ +#define PCIE_T_PERST_CLK_US 100 + /* * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> * Recommends 1ms to 10ms timeout to check L2 ready.
"Power Sequencing and Reset Signal Timings" table (section 2.9.2) in PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 5.1 indicates PERST# should be deasserted after minimum of 100us once REFCLK is stable (symbol T_PERST-CLK). Add a macro so that PCIe controller drivers can use it. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> --- drivers/pci/pci.h | 3 +++ 1 file changed, 3 insertions(+)