| Message ID | 20240301162741.765524-4-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | dt-bindings: pci: layerscape-pci: Convert to yaml format | expand |
On Fri, Mar 01, 2024 at 11:27:41AM -0500, Frank Li wrote: > Add snps,dw-pcie-ep.yaml. > > Remove context that exist in snps,dw-pcie-ep.yaml. > > Add an example for pcie-ep. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- > 1 file changed, 29 insertions(+), 25 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > index cf517e4e46a33..07965683beece 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > @@ -10,8 +10,7 @@ maintainers: > - Frank Li <Frank.Li@nxp.com> > > description: > - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP > - and thus inherits all the common properties defined in snps,dw-pcie.yaml. > + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. > > This controller derives its clocks from the Reset Configuration Word (RCW) > which is used to describe the PLL settings at the time of chip-reset. > @@ -35,31 +34,18 @@ properties: > - const: fsl,ls-pcie-ep > > reg: > - description: base addresses and lengths of the PCIe controller register blocks. > + maxItems: 2 > + > + reg-names: > + maxItems: 2 > > interrupts: > - description: A list of interrupt outputs of the controller. Must contain an > - entry for each entry in the interrupt-names property. > + minItems: 1 > + maxItems: 3 > > interrupt-names: > minItems: 1 > maxItems: 3 > - description: It could include the following entries. > - items: > - oneOf: > - - description: > - Used for interrupt line which reports AER events when > - non MSI/MSI-X/INTx mode is used. > - const: aer > - - description: > - Used for interrupt line which reports PME events when > - non MSI/MSI-X/INTx mode is used. > - const: pme > - - description: > - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) > - which has a single interrupt line for miscellaneous controller > - events(could include AER and PME events). > - const: intr > > fsl,pcie-scfg: > $ref: /schemas/types.yaml#/definitions/phandle > @@ -68,10 +54,7 @@ properties: > The second entry is the physical PCIe controller index starting from '0'. > This is used to get SCFG PEXN registers > > - dma-coherent: > - description: Indicates that the hardware IP block can ensure the coherency > - of the data transferred from/to the IP block. This can avoid the software > - cache flush/invalid actions, and improve the performance significantly > + dma-coherent: true > > big-endian: > $ref: /schemas/types.yaml#/definitions/flag > @@ -85,3 +68,24 @@ required: > - reg > - interrupt-names > > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie-ep@3400000 { > + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; > + reg = <0x00 0x03400000 0x0 0x00100000 > + 0x80 0x00000000 0x8 0x00000000>; > + reg-names = "dbi", "addr_space"; > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ PME or... > + interrupt-names = "app"; app? You seem to just be changing the names to make the example happy. What do the dts files have? You need to make those pass. Rob
On Mon, Mar 04, 2024 at 12:20:49PM -0600, Rob Herring wrote: > On Fri, Mar 01, 2024 at 11:27:41AM -0500, Frank Li wrote: > > Add snps,dw-pcie-ep.yaml. > > > > Remove context that exist in snps,dw-pcie-ep.yaml. > > > > Add an example for pcie-ep. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- > > 1 file changed, 29 insertions(+), 25 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > index cf517e4e46a33..07965683beece 100644 > > --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > @@ -10,8 +10,7 @@ maintainers: > > - Frank Li <Frank.Li@nxp.com> > > > > description: > > - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP > > - and thus inherits all the common properties defined in snps,dw-pcie.yaml. > > + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. > > > > This controller derives its clocks from the Reset Configuration Word (RCW) > > which is used to describe the PLL settings at the time of chip-reset. > > @@ -35,31 +34,18 @@ properties: > > - const: fsl,ls-pcie-ep > > > > reg: > > - description: base addresses and lengths of the PCIe controller register blocks. > > + maxItems: 2 > > + > > + reg-names: > > + maxItems: 2 > > > > interrupts: > > - description: A list of interrupt outputs of the controller. Must contain an > > - entry for each entry in the interrupt-names property. > > + minItems: 1 > > + maxItems: 3 > > > > interrupt-names: > > minItems: 1 > > maxItems: 3 > > - description: It could include the following entries. > > - items: > > - oneOf: > > - - description: > > - Used for interrupt line which reports AER events when > > - non MSI/MSI-X/INTx mode is used. > > - const: aer > > - - description: > > - Used for interrupt line which reports PME events when > > - non MSI/MSI-X/INTx mode is used. > > - const: pme > > - - description: > > - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) > > - which has a single interrupt line for miscellaneous controller > > - events(could include AER and PME events). > > - const: intr > > > > fsl,pcie-scfg: > > $ref: /schemas/types.yaml#/definitions/phandle > > @@ -68,10 +54,7 @@ properties: > > The second entry is the physical PCIe controller index starting from '0'. > > This is used to get SCFG PEXN registers > > > > - dma-coherent: > > - description: Indicates that the hardware IP block can ensure the coherency > > - of the data transferred from/to the IP block. This can avoid the software > > - cache flush/invalid actions, and improve the performance significantly > > + dma-coherent: true > > > > big-endian: > > $ref: /schemas/types.yaml#/definitions/flag > > @@ -85,3 +68,24 @@ required: > > - reg > > - interrupt-names > > > > +allOf: > > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pcie-ep@3400000 { > > + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; > > + reg = <0x00 0x03400000 0x0 0x00100000 > > + 0x80 0x00000000 0x8 0x00000000>; > > + reg-names = "dbi", "addr_space"; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ > > PME or... > > > + interrupt-names = "app"; > > app? You seem to just be changing the names to make the example happy. > What do the dts files have? You need to make those pass. It's on my plan. First need change 'regs' to 'dbi'. https://lore.kernel.org/linux-pci/20240229194559.709182-1-Frank.Li@nxp.com/ After that, I can update all dts. The second step: Change EP side interrupt-names. Frank > > Rob
On Mon, Mar 04, 2024 at 02:08:41PM -0500, Frank Li wrote: > On Mon, Mar 04, 2024 at 12:20:49PM -0600, Rob Herring wrote: > > On Fri, Mar 01, 2024 at 11:27:41AM -0500, Frank Li wrote: > > > Add snps,dw-pcie-ep.yaml. > > > > > > Remove context that exist in snps,dw-pcie-ep.yaml. > > > > > > Add an example for pcie-ep. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > --- > > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- > > > 1 file changed, 29 insertions(+), 25 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > index cf517e4e46a33..07965683beece 100644 > > > --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > @@ -10,8 +10,7 @@ maintainers: > > > - Frank Li <Frank.Li@nxp.com> > > > > > > description: > > > - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP > > > - and thus inherits all the common properties defined in snps,dw-pcie.yaml. > > > + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. > > > > > > This controller derives its clocks from the Reset Configuration Word (RCW) > > > which is used to describe the PLL settings at the time of chip-reset. > > > @@ -35,31 +34,18 @@ properties: > > > - const: fsl,ls-pcie-ep > > > > > > reg: > > > - description: base addresses and lengths of the PCIe controller register blocks. > > > + maxItems: 2 > > > + > > > + reg-names: > > > + maxItems: 2 > > > > > > interrupts: > > > - description: A list of interrupt outputs of the controller. Must contain an > > > - entry for each entry in the interrupt-names property. > > > + minItems: 1 > > > + maxItems: 3 > > > > > > interrupt-names: > > > minItems: 1 > > > maxItems: 3 > > > - description: It could include the following entries. > > > - items: > > > - oneOf: > > > - - description: > > > - Used for interrupt line which reports AER events when > > > - non MSI/MSI-X/INTx mode is used. > > > - const: aer > > > - - description: > > > - Used for interrupt line which reports PME events when > > > - non MSI/MSI-X/INTx mode is used. > > > - const: pme > > > - - description: > > > - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) > > > - which has a single interrupt line for miscellaneous controller > > > - events(could include AER and PME events). > > > - const: intr > > > > > > fsl,pcie-scfg: > > > $ref: /schemas/types.yaml#/definitions/phandle > > > @@ -68,10 +54,7 @@ properties: > > > The second entry is the physical PCIe controller index starting from '0'. > > > This is used to get SCFG PEXN registers > > > > > > - dma-coherent: > > > - description: Indicates that the hardware IP block can ensure the coherency > > > - of the data transferred from/to the IP block. This can avoid the software > > > - cache flush/invalid actions, and improve the performance significantly > > > + dma-coherent: true > > > > > > big-endian: > > > $ref: /schemas/types.yaml#/definitions/flag > > > @@ -85,3 +68,24 @@ required: > > > - reg > > > - interrupt-names > > > > > > +allOf: > > > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > + > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + pcie-ep@3400000 { > > > + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; > > > + reg = <0x00 0x03400000 0x0 0x00100000 > > > + 0x80 0x00000000 0x8 0x00000000>; > > > + reg-names = "dbi", "addr_space"; > > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ > > > > PME or... > > > > > + interrupt-names = "app"; > > > > app? You seem to just be changing the names to make the example happy. > > What do the dts files have? You need to make those pass. > > It's on my plan. > > First need change 'regs' to 'dbi'. > > https://lore.kernel.org/linux-pci/20240229194559.709182-1-Frank.Li@nxp.com/ > > After that, I can update all dts. No! I'm saying you shouldn't be changing the dts files. That's an ABI which you are likely breaking. You should adjust the binding so the dts files pass. The exception is if you know the change is safe and not going to break the ABI or the dts is just been wrong all along (e.g. missing a compatible the OS doesn't rely on). Rob
On Tue, Mar 05, 2024 at 08:37:19AM -0600, Rob Herring wrote: > On Mon, Mar 04, 2024 at 02:08:41PM -0500, Frank Li wrote: > > On Mon, Mar 04, 2024 at 12:20:49PM -0600, Rob Herring wrote: > > > On Fri, Mar 01, 2024 at 11:27:41AM -0500, Frank Li wrote: > > > > Add snps,dw-pcie-ep.yaml. > > > > > > > > Remove context that exist in snps,dw-pcie-ep.yaml. > > > > > > > > Add an example for pcie-ep. > > > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > > > --- > > > > .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- > > > > 1 file changed, 29 insertions(+), 25 deletions(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > index cf517e4e46a33..07965683beece 100644 > > > > --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml > > > > @@ -10,8 +10,7 @@ maintainers: > > > > - Frank Li <Frank.Li@nxp.com> > > > > > > > > description: > > > > - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP > > > > - and thus inherits all the common properties defined in snps,dw-pcie.yaml. > > > > + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. > > > > > > > > This controller derives its clocks from the Reset Configuration Word (RCW) > > > > which is used to describe the PLL settings at the time of chip-reset. > > > > @@ -35,31 +34,18 @@ properties: > > > > - const: fsl,ls-pcie-ep > > > > > > > > reg: > > > > - description: base addresses and lengths of the PCIe controller register blocks. > > > > + maxItems: 2 > > > > + > > > > + reg-names: > > > > + maxItems: 2 > > > > > > > > interrupts: > > > > - description: A list of interrupt outputs of the controller. Must contain an > > > > - entry for each entry in the interrupt-names property. > > > > + minItems: 1 > > > > + maxItems: 3 > > > > > > > > interrupt-names: > > > > minItems: 1 > > > > maxItems: 3 > > > > - description: It could include the following entries. > > > > - items: > > > > - oneOf: > > > > - - description: > > > > - Used for interrupt line which reports AER events when > > > > - non MSI/MSI-X/INTx mode is used. > > > > - const: aer > > > > - - description: > > > > - Used for interrupt line which reports PME events when > > > > - non MSI/MSI-X/INTx mode is used. > > > > - const: pme > > > > - - description: > > > > - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) > > > > - which has a single interrupt line for miscellaneous controller > > > > - events(could include AER and PME events). > > > > - const: intr > > > > > > > > fsl,pcie-scfg: > > > > $ref: /schemas/types.yaml#/definitions/phandle > > > > @@ -68,10 +54,7 @@ properties: > > > > The second entry is the physical PCIe controller index starting from '0'. > > > > This is used to get SCFG PEXN registers > > > > > > > > - dma-coherent: > > > > - description: Indicates that the hardware IP block can ensure the coherency > > > > - of the data transferred from/to the IP block. This can avoid the software > > > > - cache flush/invalid actions, and improve the performance significantly > > > > + dma-coherent: true > > > > > > > > big-endian: > > > > $ref: /schemas/types.yaml#/definitions/flag > > > > @@ -85,3 +68,24 @@ required: > > > > - reg > > > > - interrupt-names > > > > > > > > +allOf: > > > > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > > > > + > > > > +examples: > > > > + - | > > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > > + > > > > + soc { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + > > > > + pcie-ep@3400000 { > > > > + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; > > > > + reg = <0x00 0x03400000 0x0 0x00100000 > > > > + 0x80 0x00000000 0x8 0x00000000>; > > > > + reg-names = "dbi", "addr_space"; > > > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ > > > > > > PME or... > > > > > > > + interrupt-names = "app"; > > > > > > app? You seem to just be changing the names to make the example happy. > > > What do the dts files have? You need to make those pass. > > > > It's on my plan. > > > > First need change 'regs' to 'dbi'. > > > > https://lore.kernel.org/linux-pci/20240229194559.709182-1-Frank.Li@nxp.com/ > > > > After that, I can update all dts. > > No! > > I'm saying you shouldn't be changing the dts files. That's an ABI > which you are likely breaking. You should adjust the binding so the dts > files pass. The exception is if you know the change is safe and not > going to break the ABI or the dts is just been wrong all along (e.g. > missing a compatible the OS doesn't rely on). The problem is that I have not method to make dts check without warning. If using snps,dw-pcie-ep.yaml/snps,dw-pcie.yaml, it always complain 'regs' and 'pme'. If update snps,dw-pcie-ep-.yaml/snps,dw-pcie.yaml, there are two name 'regs' and 'dbi' will be the same thing. it should be bad. If don't included snps,dw-pcie-ep-.yaml/snps,dw-pcie.yaml, I have to duplicate most parts, which already in these files. If you have good method, let me know. Frank > > Rob
diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index cf517e4e46a33..07965683beece 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -10,8 +10,7 @@ maintainers: - Frank Li <Frank.Li@nxp.com> description: - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. @@ -35,31 +34,18 @@ properties: - const: fsl,ls-pcie-ep reg: - description: base addresses and lengths of the PCIe controller register blocks. + maxItems: 2 + + reg-names: + maxItems: 2 interrupts: - description: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -68,10 +54,7 @@ properties: The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: - description: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly + dma-coherent: true big-endian: $ref: /schemas/types.yaml#/definitions/flag @@ -85,3 +68,24 @@ required: - reg - interrupt-names +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "dbi", "addr_space"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ + interrupt-names = "app"; + }; + }; +...
Add snps,dw-pcie-ep.yaml. Remove context that exist in snps,dw-pcie-ep.yaml. Add an example for pcie-ep. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- 1 file changed, 29 insertions(+), 25 deletions(-)