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PCI: rockchip-ep: Remove wrong mask on subsys_vendor_id

Message ID 20240403144508.489835-1-rick.wertenbroek@gmail.com (mailing list archive)
State Accepted
Delegated to: Krzysztof Wilczyński
Headers show
Series PCI: rockchip-ep: Remove wrong mask on subsys_vendor_id | expand

Commit Message

Rick Wertenbroek April 3, 2024, 2:45 p.m. UTC
Remove wrong mask on subsys_vendor_id. Both the Vendor ID and Subsystem
Vendor ID are u16 variables and are written to a u32 register of the
controller. The Subsystem Vendor ID was always 0 because the u16 value
was masked incorrectly with GENMASK(31,16) resulting in all lower 16
bits being set to 0 prior to the shift.

Remove both masks as they are unnecessary and set the register correctly
i.e., the lower 16-bits are the Vendor ID and the upper 16-bits are the
Subsystem Vendor ID.

This is documented in the RK3399 TRM section 17.6.7.1.17

Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Cc: stable@vger.kernel.org
---
 drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Rick Wertenbroek April 3, 2024, 2:55 p.m. UTC | #1
On Wed, Apr 3, 2024 at 4:45 PM Rick Wertenbroek
<rick.wertenbroek@gmail.com> wrote:
>
> Remove wrong mask on subsys_vendor_id. Both the Vendor ID and Subsystem
> Vendor ID are u16 variables and are written to a u32 register of the
> controller. The Subsystem Vendor ID was always 0 because the u16 value
> was masked incorrectly with GENMASK(31,16) resulting in all lower 16
> bits being set to 0 prior to the shift.
>
> Remove both masks as they are unnecessary and set the register correctly
> i.e., the lower 16-bits are the Vendor ID and the upper 16-bits are the
> Subsystem Vendor ID.
>
> This is documented in the RK3399 TRM section 17.6.7.1.17
>
> Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> index c9046e97a1d2..37d4bcb8bd5b 100644
> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -98,10 +98,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
>
>         /* All functions share the same vendor ID with function 0 */
>         if (fn == 0) {
> -               u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
> -                              (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
> -
> -               rockchip_pcie_write(rockchip, vid_regs,
> +               rockchip_pcie_write(rockchip,
> +                                   hdr->vendorid |
> +                                   hdr->subsys_vendor_id << 16,
>                                     PCIE_CORE_CONFIG_VENDOR);
>         }
>
> --
> 2.25.1
>

This patch was tested on linux next-20240403.

The PCI endpoint test function was used and an arbitrary value e.g., 0x1234
was written to /sys/kernel/config/pci_ep/functions/pci_epf_test/pci_epf_test.0/subsys_vendor_id

This value was then verified with lspci -x / lspci -v on a host
computer acting as PCI root complex.

Cheers,
Rick
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Patch

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index c9046e97a1d2..37d4bcb8bd5b 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -98,10 +98,9 @@  static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
 
 	/* All functions share the same vendor ID with function 0 */
 	if (fn == 0) {
-		u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
-			       (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
-
-		rockchip_pcie_write(rockchip, vid_regs,
+		rockchip_pcie_write(rockchip,
+				    hdr->vendorid |
+				    hdr->subsys_vendor_id << 16,
 				    PCIE_CORE_CONFIG_VENDOR);
 	}