| Message ID | 20240528134839.8817-2-cassel@kernel.org (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: dwc: ep: Enforce DWC specific 64-bit BAR limitiation | expand |
On Tue, May 28, 2024 at 03:48:40PM +0200, Niklas Cassel wrote: > From the DWC EP databook 5.96a, section "3.5.7.1.4 General Rules for BAR > Setup (Fixed Mask or Programmable Mask Schemes Only)": > > "Any pair (for example BARs 0 and 1) can be configured as one 64-bit BAR, > two 32-bit BARs, or one 32-bit BAR." > > "BAR pairs cannot overlap to form a 64-bit BAR. For example, you cannot > combine BARs 1 and 2 to form a 64-bit BAR." > > While this limitation does exist in some other PCI endpoint controllers, > e.g. cdns_pcie_ep_set_bar(), the limitation does not appear to be defined > in the PCIe specification itself, thus add an explicit check for this in > dw_pcie_ep_set_bar() (rather than pci_epc_set_bar()). > > Signed-off-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index f22252699548..42db3c3bbe96 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -227,6 +227,13 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, > int ret, type; > u32 reg; > > + /* > + * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs > + * 1 and 2 to form a 64-bit BAR. > + */ > + if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) > + return -EINVAL; > + > reg = PCI_BASE_ADDRESS_0 + (4 * bar); > > if (!(flags & PCI_BASE_ADDRESS_SPACE)) > -- > 2.45.1 >
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f22252699548..42db3c3bbe96 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -227,6 +227,13 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, int ret, type; u32 reg; + /* + * DWC does not allow BAR pairs to overlap, e.g. you cannot combine BARs + * 1 and 2 to form a 64-bit BAR. + */ + if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) + return -EINVAL; + reg = PCI_BASE_ADDRESS_0 + (4 * bar); if (!(flags & PCI_BASE_ADDRESS_SPACE))
From the DWC EP databook 5.96a, section "3.5.7.1.4 General Rules for BAR Setup (Fixed Mask or Programmable Mask Schemes Only)": "Any pair (for example BARs 0 and 1) can be configured as one 64-bit BAR, two 32-bit BARs, or one 32-bit BAR." "BAR pairs cannot overlap to form a 64-bit BAR. For example, you cannot combine BARs 1 and 2 to form a 64-bit BAR." While this limitation does exist in some other PCI endpoint controllers, e.g. cdns_pcie_ep_set_bar(), the limitation does not appear to be defined in the PCIe specification itself, thus add an explicit check for this in dw_pcie_ep_set_bar() (rather than pci_epc_set_bar()). Signed-off-by: Niklas Cassel <cassel@kernel.org> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++++ 1 file changed, 7 insertions(+)