| Message ID | 20240924101444.3933828-3-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Tue, Sep 24, 2024 at 03:14:40AM -0700, Qiang Yu wrote: > OPP table is a generic property that is also required by other qcom > platforms. Hence move this property to qcom,pcie-common.yaml so that PCIe > on other qcom platforms is able to adjust power domain performance state > and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ > Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ---- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > index 704c0f58eea5..3c6430fe9331 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > @@ -78,6 +78,10 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + operating-points-v2: true > + opp-table: > + type: object > + > required: > - reg > - reg-names > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > index 46bd59eefadb..6e0a6d8f0ed0 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > @@ -70,10 +70,6 @@ properties: > - const: msi7 > - const: global > > - operating-points-v2: true > - opp-table: > - type: object > - > resets: > maxItems: 1 > > -- > 2.34.1 >
On 24/09/2024 12:14, Qiang Yu wrote: > OPP table is a generic property that is also required by other qcom > platforms. Hence move this property to qcom,pcie-common.yaml so that PCIe > on other qcom platforms is able to adjust power domain performance state > and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 704c0f58eea5..3c6430fe9331 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -78,6 +78,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index 46bd59eefadb..6e0a6d8f0ed0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -70,10 +70,6 @@ properties: - const: msi7 - const: global - operating-points-v2: true - opp-table: - type: object - resets: maxItems: 1
OPP table is a generic property that is also required by other qcom platforms. Hence move this property to qcom,pcie-common.yaml so that PCIe on other qcom platforms is able to adjust power domain performance state and ICC peak bw according to PCIe gen speed and link width. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-)