| Message ID | 20241018182247.41130-2-james.quinlan@broadcom.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | RFC: Need feedback on PCI dt binding property | expand |
On Fri, Oct 18, 2024 at 02:22:45PM -0400, Jim Quinlan wrote: > Support configuration of the GEN3 preset equalization settings, aka the > Lane Equalization Control Register(s) of the Secondary PCI Express > Extended Capability. These registers are of type HwInit/RsvdP and > typically set by FW. In our case they are set by our RC host bridge > driver using internal registers. > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > --- > .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > index 0925c520195a..f965ad57f32f 100644 > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml > @@ -104,6 +104,18 @@ properties: > minItems: 1 > maxItems: 3 > > + brcm,gen3-eq-presets: > + description: | > + A u16 array giving the GEN3 equilization presets, one for each lane. > + These values are destined for the 16bit registers known as the > + Lane Equalization Control Register(s) of the Secondary PCI Express > + Extended Capability. In the array, lane 0 is first term, lane 1 next, > + etc. The contents of the entries reflect what is necessary for > + the current board and SoC, and the details of each preset are > + described in Section 7.27.4 of the PCI base spec, Revision 3.0. s/equilization/equalization/ The spec citation ("PCI base spec r3.0") isn't quite right since Conventional PCI doesn't have lanes. These registers *are* defined in PCIe r3.0, sec 7.27.4, but that's 14 years old. It would be more helpful to use a current spec version like PCIe r6.2, sec 7.7.3.4. Since there's nothing about these registers that is brcm-specific (other than the fact that they are typically set by firmware on non-brcm platforms), it would be nice if we could give it a non-brcm name. Similarly, I think it would be nice to drop "gen3" from the name (and the description). The registers *were* added in PCIe r3.0, which also added the 8 GT/s rate, and the description in PCIe r6.2, sec 7.7.3.4 does mention 8.0 GT/s specifically, but sec 4.2.4 says equalization applies to "8.0 GT/s and higher data rates," so it's definitely not limited to gen3. Bjorn
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 0925c520195a..f965ad57f32f 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -104,6 +104,18 @@ properties: minItems: 1 maxItems: 3 + brcm,gen3-eq-presets: + description: | + A u16 array giving the GEN3 equilization presets, one for each lane. + These values are destined for the 16bit registers known as the + Lane Equalization Control Register(s) of the Secondary PCI Express + Extended Capability. In the array, lane 0 is first term, lane 1 next, + etc. The contents of the entries reflect what is necessary for + the current board and SoC, and the details of each preset are + described in Section 7.27.4 of the PCI base spec, Revision 3.0. + + $ref: /schemas/types.yaml#/definitions/uint16-array + required: - compatible - reg
Support configuration of the GEN3 preset equalization settings, aka the Lane Equalization Control Register(s) of the Secondary PCI Express Extended Capability. These registers are of type HwInit/RsvdP and typically set by FW. In our case they are set by our RC host bridge driver using internal registers. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)