| Message ID | 20241224-enable_ecam-v2-2-43daef68a901@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Manivannan Sadhasivam |
| Headers | show |
| Series | PCI: dwc: Add ECAM support with iATU configuration | expand |
On 24.12.2024 3:10 PM, Krishna Chaitanya Chundru wrote: > From: Krishna chaitanya chundru <quic_krichai@quicinc.com> > > The current implementation requires iATU for every configuration > space access which increases latency & cpu utilization. > > Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, > which shifts/maps the BDF (bits [31:16] of the third header DWORD, which > would be matched against the Base and Limit addresses) of the incoming > CfgRd0/CfgWr0 down to bits[27:12]of the translated address. > > Configuring iATU in config shift feature enables ECAM feature to access the > config space, which avoids iATU configuration for every config access. > > Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. > > As DBI comes under config space, this avoids remapping of DBI space > separately. Instead, it uses the mapped config space address returned from > ECAM initialization. Change the order of dw_pcie_get_resources() execution > to achieve this. > > Enable the ECAM feature if the config space size is equal to size required > to represent number of buses in the bus range property, add a function > which checks this. The DWC glue drivers uses this function and decide to > enable ECAM mode or not. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > drivers/pci/controller/dwc/Kconfig | 1 + > drivers/pci/controller/dwc/pcie-designware-host.c | 136 +++++++++++++++++++--- > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > drivers/pci/controller/dwc/pcie-designware.h | 11 ++ > 4 files changed, 130 insertions(+), 20 deletions(-) > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index b6d6778b0698..73c3aed6b60a 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -9,6 +9,7 @@ config PCIE_DW > config PCIE_DW_HOST > bool > select PCIE_DW > + select PCI_HOST_COMMON > > config PCIE_DW_EP > bool > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index d2291c3ceb8b..4e07fefe12e1 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -418,6 +418,61 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) > } > } > > +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct dw_pcie_ob_atu_cfg atu = {0}; > + struct resource_entry *bus; > + int ret, bus_range_max; resource_size_t for bus_range_max since you feed it the ouput of resource_size() > + > + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); > + > + /* > + * Root bus under the root port doesn't require any iATU configuration > + * as DBI space will represent Root bus configuration space. > + * Immediate bus under Root Bus, needs type 0 iATU configuration and > + * remaining buses need type 1 iATU configuration. > + */ > + atu.index = 0; > + atu.type = PCIE_ATU_TYPE_CFG0; > + atu.cpu_addr = pp->cfg0_base + SZ_1M; > + atu.size = SZ_1M; > + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; > + ret = dw_pcie_prog_outbound_atu(pci, &atu); > + if (ret) > + return ret; > + > + bus_range_max = resource_size(bus->res); > + > + /* Configure remaining buses in type 1 iATU configuration */ > + atu.index = 1; > + atu.type = PCIE_ATU_TYPE_CFG1; > + atu.cpu_addr = pp->cfg0_base + SZ_2M; > + atu.size = (SZ_1M * (bus_range_max - 2)); This explodes badly with: bus-range = <0 0>; > + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; > + return dw_pcie_prog_outbound_atu(pci, &atu); A newline before the return statement would make it prettier [...] > +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct platform_device *pdev = to_platform_device(pci->dev); > + struct resource *config_res, *bus_range; > + u64 bus_config_space_count; > + > + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; > + if (!bus_range) > + return false; > + > + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); > + if (!config_res) > + return false; > + > + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; > + if (resource_size(bus_range) > bus_config_space_count) > + return false; > + > + return true; return bus_config_space_count <= resource_size(bus_range); Konrad
On 12/30/2024 8:34 PM, Konrad Dybcio wrote: > On 24.12.2024 3:10 PM, Krishna Chaitanya Chundru wrote: >> From: Krishna chaitanya chundru <quic_krichai@quicinc.com> >> >> The current implementation requires iATU for every configuration >> space access which increases latency & cpu utilization. >> >> Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, >> which shifts/maps the BDF (bits [31:16] of the third header DWORD, which >> would be matched against the Base and Limit addresses) of the incoming >> CfgRd0/CfgWr0 down to bits[27:12]of the translated address. >> >> Configuring iATU in config shift feature enables ECAM feature to access the >> config space, which avoids iATU configuration for every config access. >> >> Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. >> >> As DBI comes under config space, this avoids remapping of DBI space >> separately. Instead, it uses the mapped config space address returned from >> ECAM initialization. Change the order of dw_pcie_get_resources() execution >> to achieve this. >> >> Enable the ECAM feature if the config space size is equal to size required >> to represent number of buses in the bus range property, add a function >> which checks this. The DWC glue drivers uses this function and decide to >> enable ECAM mode or not. >> >> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> >> --- >> drivers/pci/controller/dwc/Kconfig | 1 + >> drivers/pci/controller/dwc/pcie-designware-host.c | 136 +++++++++++++++++++--- >> drivers/pci/controller/dwc/pcie-designware.c | 2 +- >> drivers/pci/controller/dwc/pcie-designware.h | 11 ++ >> 4 files changed, 130 insertions(+), 20 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig >> index b6d6778b0698..73c3aed6b60a 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -9,6 +9,7 @@ config PCIE_DW >> config PCIE_DW_HOST >> bool >> select PCIE_DW >> + select PCI_HOST_COMMON >> >> config PCIE_DW_EP >> bool >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index d2291c3ceb8b..4e07fefe12e1 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -418,6 +418,61 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) >> } >> } >> >> +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + struct dw_pcie_ob_atu_cfg atu = {0}; >> + struct resource_entry *bus; >> + int ret, bus_range_max; > resource_size_t for bus_range_max since you feed it the ouput of > resource_size() > >> + >> + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); >> + >> + /* >> + * Root bus under the root port doesn't require any iATU configuration >> + * as DBI space will represent Root bus configuration space. >> + * Immediate bus under Root Bus, needs type 0 iATU configuration and >> + * remaining buses need type 1 iATU configuration. >> + */ >> + atu.index = 0; >> + atu.type = PCIE_ATU_TYPE_CFG0; >> + atu.cpu_addr = pp->cfg0_base + SZ_1M; >> + atu.size = SZ_1M; >> + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; >> + ret = dw_pcie_prog_outbound_atu(pci, &atu); >> + if (ret) >> + return ret; >> + >> + bus_range_max = resource_size(bus->res); >> + >> + /* Configure remaining buses in type 1 iATU configuration */ >> + atu.index = 1; >> + atu.type = PCIE_ATU_TYPE_CFG1; >> + atu.cpu_addr = pp->cfg0_base + SZ_2M; >> + atu.size = (SZ_1M * (bus_range_max - 2)); > This explodes badly with: > > bus-range = <0 0>; The bus range = <0 0> is not a valid configuration but with bus-range = <0 1> it will be a issue I will update the logic next series, thanks for pointing it out. - Krishna Chaitanya. > >> + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; >> + return dw_pcie_prog_outbound_atu(pci, &atu); > A newline before the return statement would make it prettier > > [...] > >> +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + struct platform_device *pdev = to_platform_device(pci->dev); >> + struct resource *config_res, *bus_range; >> + u64 bus_config_space_count; >> + >> + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; >> + if (!bus_range) >> + return false; >> + >> + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); >> + if (!config_res) >> + return false; >> + >> + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; >> + if (resource_size(bus_range) > bus_config_space_count) >> + return false; >> + >> + return true; > return bus_config_space_count <= resource_size(bus_range); > > Konrad
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..73c3aed6b60a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -9,6 +9,7 @@ config PCIE_DW config PCIE_DW_HOST bool select PCIE_DW + select PCI_HOST_COMMON config PCIE_DW_EP bool diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d2291c3ceb8b..4e07fefe12e1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,61 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) } } +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = {0}; + struct resource_entry *bus; + int ret, bus_range_max; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Root bus under the root port doesn't require any iATU configuration + * as DBI space will represent Root bus configuration space. + * Immediate bus under Root Bus, needs type 0 iATU configuration and + * remaining buses need type 1 iATU configuration. + */ + atu.index = 0; + atu.type = PCIE_ATU_TYPE_CFG0; + atu.cpu_addr = pp->cfg0_base + SZ_1M; + atu.size = SZ_1M; + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max = resource_size(bus->res); + + /* Configure remaining buses in type 1 iATU configuration */ + atu.index = 1; + atu.type = PCIE_ATU_TYPE_CFG1; + atu.cpu_addr = pp->cfg0_base + SZ_2M; + atu.size = (SZ_1M * (bus_range_max - 2)); + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *res) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct resource_entry *bus; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base = pp->cfg->win; + pci->dbi_phys_addr = res->start; + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -431,19 +486,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) raw_spin_lock_init(&pp->lock); - ret = dw_pcie_get_resources(pci); - if (ret) - return ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); - if (res) { - pp->cfg0_size = resource_size(res); - pp->cfg0_base = res->start; - - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); - } else { + if (!res) { dev_err(dev, "Missing *config* reg space\n"); return -ENODEV; } @@ -454,6 +498,31 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->bridge = bridge; + pp->cfg0_size = resource_size(res); + pp->cfg0_base = res->start; + + if (pp->ecam_mode) { + ret = dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; + bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata = pp->cfg; + pp->cfg->priv = pp; + } else { + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; + bridge->sysdata = pp; + } + + ret = dw_pcie_get_resources(pci); + if (ret) + goto err_free_ecam; + /* Get the I/O range from DT */ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); if (win) { @@ -462,14 +531,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base = pci_pio_to_address(win->res->start); } - /* Set default bus ops */ - bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_child_pcie_ops; - if (pp->ops->init) { ret = pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } if (pci_msi_enabled()) { @@ -504,6 +569,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pp->ecam_mode) { + ret = dw_pcie_config_ecam_iatu(pp); + if (ret) + goto err_free_msi; + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -533,8 +604,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); - bridge->sysdata = pp; - ret = pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -558,6 +627,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -578,6 +651,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); @@ -985,3 +1061,25 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci) return ret; } EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); + +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + struct resource *config_res, *bus_range; + u64 bus_config_space_count; + + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; + if (!bus_range) + return false; + + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (!config_res) + return false; + + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; + if (resource_size(bus_range) > bus_config_space_count) + return false; + + return true; +} diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..63d36676f858 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -509,7 +509,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - val = PCIE_ATU_ENABLE; + val = PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type == PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..41022f06572e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include <linux/irq.h> #include <linux/msi.h> #include <linux/pci.h> +#include <linux/pci-ecam.h> #include <linux/reset.h> #include <linux/pci-epc.h> @@ -171,6 +172,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -342,6 +344,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; u8 code; u8 routing; + u32 ctrl2; u64 cpu_addr; u64 pci_addr; u64 size; @@ -379,6 +382,8 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool ecam_mode; + struct pci_config_window *cfg; }; struct dw_pcie_ep_ops { @@ -685,6 +690,7 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp); int dw_pcie_allocate_domains(struct dw_pcie_rp *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) { @@ -715,6 +721,11 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static inline bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + return 0; +} #endif #ifdef CONFIG_PCIE_DW_EP