Message ID | 20250123181932.935870-3-matthew.gerlach@linux.intel.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Krzysztof WilczyĆski |
Headers | show |
Series | Add PCIe Root Port support for Agilex family of chips | expand |
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 1235ba5a9865..144fe74e929e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -152,7 +152,7 @@ usbphy0: usbphy { compatible = "usb-nop-xceiv"; }; - soc@0 { + soc0: soc@0 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus";
Add a label to the soc@0 device tree node. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v3: - Remove accepted patches from patch set. --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)