| Message ID | 20250207-ecam_v4-v4-3-94b5d5ec5017@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: dwc: Add ECAM support with iATU configuration | expand |
On Fri, Feb 07, 2025 at 04:58:58AM +0530, Krishna Chaitanya Chundru wrote: > dw_pcie_ecam_supported() needs to read bus-range to find the maximum > bus range value. The devm_pci_alloc_host_bridge() is already reading > bus range and storing it in host bridge.If devm_pci_alloc_host_bridge() What do you mean by 'storig in host bridge' here? Mention the exact structure name if that's what you are referring to. > moved to start of the controller probe, the dt reading can be avoided > and use values stored in the host bridge. Same here. > > Allow DWC glue drivers to allocate the host bridge, avoiding redundant > device tree reads primarily in dw_pcie_ecam_supported(). > This makes little sense to me. By this change, you essentially want DWC glue drivers to call devm_pci_alloc_host_bridge() just to get rid of one range parsing. I'd suggest to move dw_pcie_ecam_supported() inside dw_pcie_host_init() and call after devm_pci_alloc_host_bridge(). This way, the glue drivers can rely on DWC core to detect ECAM like other resources. And the API could be renamed as dw_pcie_ecam_detect() to match other resource detection like iATU, eDMA. More in patch 4. - Mani > Suggested-by: Bjorn Helgaas <bhelgaas@google.com> > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 826ff9338646..a18cb1e411e4 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > struct device *dev = pci->dev; > struct device_node *np = dev->of_node; > struct platform_device *pdev = to_platform_device(dev); > + struct pci_host_bridge *bridge = pp->bridge; > struct resource_entry *win; > - struct pci_host_bridge *bridge; > struct resource *res; > int ret; > > @@ -527,7 +527,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (!bridge) > return -ENOMEM; > > - pp->bridge = bridge; > + if (!pp->bridge) { > + bridge = devm_pci_alloc_host_bridge(dev, 0); > + if (!bridge) > + return -ENOMEM; > + pp->bridge = bridge; > + } > > /* Get the I/O range from DT */ > win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); > > -- > 2.34.1 >
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 826ff9338646..a18cb1e411e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct device *dev = pci->dev; struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); + struct pci_host_bridge *bridge = pp->bridge; struct resource_entry *win; - struct pci_host_bridge *bridge; struct resource *res; int ret; @@ -527,7 +527,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (!bridge) return -ENOMEM; - pp->bridge = bridge; + if (!pp->bridge) { + bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; + pp->bridge = bridge; + } /* Get the I/O range from DT */ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
dw_pcie_ecam_supported() needs to read bus-range to find the maximum bus range value. The devm_pci_alloc_host_bridge() is already reading bus range and storing it in host bridge.If devm_pci_alloc_host_bridge() moved to start of the controller probe, the dt reading can be avoided and use values stored in the host bridge. Allow DWC glue drivers to allocate the host bridge, avoiding redundant device tree reads primarily in dw_pcie_ecam_supported(). Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)