diff mbox series

[v6,4/7] arm64: dts: agilex: refactor shared dts into dtsi

Message ID 20250211151725.4133582-5-matthew.gerlach@linux.intel.com (mailing list archive)
State Superseded
Delegated to: Krzysztof Wilczyński
Headers show
Series Add PCIe Root Port support for Agilex family of chips | expand

Commit Message

Matthew Gerlach Feb. 11, 2025, 3:17 p.m. UTC 
Move common device tree from socfpga_agilex_socdk*.dts to
socfpga_agilex_socdk.dtsi.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
 ---
 v6:
  - New patch to series.
---
 .../boot/dts/intel/socfpga_agilex_socdk.dts   | 62 +-----------------
 .../boot/dts/intel/socfpga_agilex_socdk.dtsi  | 65 +++++++++++++++++++
 .../dts/intel/socfpga_agilex_socdk_nand.dts   | 62 +-----------------
 3 files changed, 67 insertions(+), 122 deletions(-)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi

Comments

Krzysztof Kozlowski Feb. 12, 2025, 5:59 a.m. UTC | #1 
On 11/02/2025 16:17, Matthew Gerlach wrote:
> Move common device tree from socfpga_agilex_socdk*.dts to
> socfpga_agilex_socdk.dtsi.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>  ---




> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
> new file mode 100644
> index 000000000000..e0f3ff60aa33
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier:     GPL-2.0
> +/*
> + * Copyright (C) 2019, Intel Corporation
> + */
> +
> +/ {
> +	model = "SoCFPGA Agilex SoCDK";
> +	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";

That's not correct. Compatible is not being shared between different
boards. Different boards have different compatible.



Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..a970f612333a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -3,50 +3,7 @@ 
  * Copyright (C) 2019, Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
-
-/ {
-	model = "SoCFPGA Agilex SoCDK";
-	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		ethernet2 = &gmac2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led0 {
-			label = "hps_led0";
-			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
-		};
-
-		led1 {
-			label = "hps_led1";
-			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
-		};
-
-		led2 {
-			label = "hps_led2";
-			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* We expect the bootloader to fill in the reg */
-		reg = <0 0x80000000 0 0>;
-	};
-};
-
-&gpio1 {
-	status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
 
 &gmac0 {
 	status = "okay";
@@ -86,23 +43,6 @@  &mmc {
 	clk-phase-sd-hs = <0>, <135>;
 };
 
-&osc1 {
-	clock-frequency = <25000000>;
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-	disable-over-current;
-};
-
-&watchdog0 {
-	status = "okay";
-};
-
 &qspi {
 	status = "okay";
 	flash@0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
new file mode 100644
index 000000000000..e0f3ff60aa33
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
@@ -0,0 +1,65 @@ 
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/ {
+	model = "SoCFPGA Agilex SoCDK";
+	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 0f9020bd0c52..53a533cd2789 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -3,50 +3,7 @@ 
  * Copyright (C) 2019, Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
-
-/ {
-	model = "SoCFPGA Agilex SoCDK";
-	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
-	aliases {
-		serial0 = &uart0;
-		ethernet0 = &gmac0;
-		ethernet1 = &gmac1;
-		ethernet2 = &gmac2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led0 {
-			label = "hps_led0";
-			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
-		};
-
-		led1 {
-			label = "hps_led1";
-			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
-		};
-
-		led2 {
-			label = "hps_led2";
-			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* We expect the bootloader to fill in the reg */
-		reg = <0 0x80000000 0 0>;
-	};
-};
-
-&gpio1 {
-	status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
 
 &gmac2 {
 	status = "okay";
@@ -97,20 +54,3 @@  partition@200000 {
 		};
 	};
 };
-
-&osc1 {
-	clock-frequency = <25000000>;
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-	disable-over-current;
-};
-
-&watchdog0 {
-	status = "okay";
-};