| Message ID | 20250211192444.2292833-6-terry.bowman@amd.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Enable CXL PCIe port protocol error handling and logging | expand |
On Tue, Feb 11, 2025 at 01:24:32PM -0600, Terry Bowman wrote: > The AER service driver supports handling Downstream Port Protocol Errors in > Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same > functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) > mode.[1] > > CXL and PCIe Protocol Error handling have different requirements that > necessitate a separate handling path. The AER service driver may try to > recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not > suitable for CXL PCIe Port devices because of potential for system memory > corruption. Instead, CXL Protocol Error handling must use a kernel panic > in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol > Error handling does not panic the kernel in response to a UCE. > > Introduce a separate path for CXL Protocol Error handling in the AER > service driver. This will allow CXL Protocol Errors to use CXL specific > handling instead of PCIe handling. Add the CXL specific changes without > affecting or adding functionality in the PCIe handling. > > Make this update alongside the existing Downstream Port RCH error handling > logic, extending support to CXL PCIe Ports in VH mode. > > Remove is_internal_error(). is_internal_error() was used to determine if > an AER error was a CXL error. Instead, now rely on pcie_is_cxl_port() to > indicate the error is a CXL error. > > The uncorrectable error (UCE) handling will be added in a future patch. > > [1] CXL 3.1 Spec, 12.2.2 CXL Root Ports, Downstream Switch Ports, and > Upstream Switch Ports > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> > --- > drivers/pci/pcie/aer.c | 47 ++++++++++++++++++++++++++++-------------- > 1 file changed, 32 insertions(+), 15 deletions(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index f99a1c6fb274..34ec0958afff 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -989,14 +989,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) > return (pcie_ports_native || host->native_aer); > } > > -static bool is_internal_error(struct aer_err_info *info) > -{ > - if (info->severity == AER_CORRECTABLE) > - return info->status & PCI_ERR_COR_INTERNAL; > - > - return info->status & PCI_ERR_UNC_INTN; > -} > - > static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) > { > struct aer_err_info *info = (struct aer_err_info *)data; > @@ -1033,9 +1025,23 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) > * RCH's downstream port. Check and handle them in the CXL.mem > * device driver. > */ > - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && > - is_internal_error(info)) > - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) > + return pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); > + > + if (info->severity == AER_CORRECTABLE) { > + struct pci_driver *pdrv = dev->driver; > + int aer = dev->aer_cap; > + > + if (aer) > + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, > + info->status); > + > + if (pdrv && pdrv->cxl_err_handler && > + pdrv->cxl_err_handler->cor_error_detected) > + pdrv->cxl_err_handler->cor_error_detected(dev); > + > + pcie_clear_device_status(dev); > + } > } > > static int handles_cxl_error_iter(struct pci_dev *dev, void *data) > @@ -1053,9 +1059,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) > { > bool handles_cxl = false; > > - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && > - pcie_aer_is_native(dev)) > + if (!pcie_aer_is_native(dev)) > + return false; > + > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) > pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); > + else > + handles_cxl = pcie_is_cxl_port(dev); > > return handles_cxl; > } > @@ -1073,6 +1083,10 @@ static void cxl_enable_internal_errors(struct pci_dev *dev) > static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } > static inline void cxl_handle_error(struct pci_dev *dev, > struct aer_err_info *info) { } > +static bool handles_cxl_errors(struct pci_dev *dev) > +{ > + return false; > +} > #endif > > /** > @@ -1110,8 +1124,11 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) > > static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) > { > - cxl_handle_error(dev, info); > - pci_aer_handle_error(dev, info); > + if (handles_cxl_errors(dev)) > + cxl_handle_error(dev, info); > + else > + pci_aer_handle_error(dev, info); > + > pci_dev_put(dev); > } > > -- > 2.34.1 >
Terry Bowman wrote: > The AER service driver supports handling Downstream Port Protocol Errors in > Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same > functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) > mode.[1] > > CXL and PCIe Protocol Error handling have different requirements that > necessitate a separate handling path. The AER service driver may try to > recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not > suitable for CXL PCIe Port devices because of potential for system memory > corruption. Instead, CXL Protocol Error handling must use a kernel panic > in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol > Error handling does not panic the kernel in response to a UCE. > > Introduce a separate path for CXL Protocol Error handling in the AER > service driver. This will allow CXL Protocol Errors to use CXL specific > handling instead of PCIe handling. Add the CXL specific changes without > affecting or adding functionality in the PCIe handling. > > Make this update alongside the existing Downstream Port RCH error handling > logic, extending support to CXL PCIe Ports in VH mode. > > Remove is_internal_error(). is_internal_error() was used to determine if > an AER error was a CXL error. Instead, now rely on pcie_is_cxl_port() to > indicate the error is a CXL error. Wait, pcie_is_cxl_port() in isolation is insufficient, right? In other words, I would expect that when the response may escalate to panic() that the code should be reasonably certain that this *is* a CXL error. At a minimum that is: pcie_is_cxl_port() && is_internal_error() ...or am I missing something that it makes it unlikely that a standard PCIe error or other internal error type will not be thrown by a pcie_is_cxl_port() device?
On 2/11/2025 5:58 PM, Dan Williams wrote: > Terry Bowman wrote: >> The AER service driver supports handling Downstream Port Protocol Errors in >> Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same >> functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) >> mode.[1] >> >> CXL and PCIe Protocol Error handling have different requirements that >> necessitate a separate handling path. The AER service driver may try to >> recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not >> suitable for CXL PCIe Port devices because of potential for system memory >> corruption. Instead, CXL Protocol Error handling must use a kernel panic >> in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol >> Error handling does not panic the kernel in response to a UCE. >> >> Introduce a separate path for CXL Protocol Error handling in the AER >> service driver. This will allow CXL Protocol Errors to use CXL specific >> handling instead of PCIe handling. Add the CXL specific changes without >> affecting or adding functionality in the PCIe handling. >> >> Make this update alongside the existing Downstream Port RCH error handling >> logic, extending support to CXL PCIe Ports in VH mode. >> >> Remove is_internal_error(). is_internal_error() was used to determine if >> an AER error was a CXL error. Instead, now rely on pcie_is_cxl_port() to >> indicate the error is a CXL error. > Wait, pcie_is_cxl_port() in isolation is insufficient, right? In other > words, I would expect that when the response may escalate to panic() > that the code should be reasonably certain that this *is* a CXL error. > At a minimum that is: > > pcie_is_cxl_port() && is_internal_error() > > ...or am I missing something that it makes it unlikely that a standard > PCIe error or other internal error type will not be thrown by a > pcie_is_cxl_port() device? I thought it was sufficient. In the CXL path the AER is logged. The PCIe handlers are not called but then again the portbus driver doesn't implement a CE handler and the UCE handler only updates the return result. That applies to all port devices. And obviously CXL RAS is logged in the CXL path. If the CXL device errors are handled in the PCIe path then CXL RAS will not be logged. I have changed directions to implement what you want. I'm only replying here to explain why I implemented as I did. Terry
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f99a1c6fb274..34ec0958afff 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -989,14 +989,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity == AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} - static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { struct aer_err_info *info = (struct aer_err_info *)data; @@ -1033,9 +1025,23 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) * RCH's downstream port. Check and handle them in the CXL.mem * device driver. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) + return pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + + if (info->severity == AER_CORRECTABLE) { + struct pci_driver *pdrv = dev->driver; + int aer = dev->aer_cap; + + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); + + if (pdrv && pdrv->cxl_err_handler && + pdrv->cxl_err_handler->cor_error_detected) + pdrv->cxl_err_handler->cor_error_detected(dev); + + pcie_clear_device_status(dev); + } } static int handles_cxl_error_iter(struct pci_dev *dev, void *data) @@ -1053,9 +1059,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl = false; - if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(dev)) + if (!pcie_aer_is_native(dev)) + return false; + + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); + else + handles_cxl = pcie_is_cxl_port(dev); return handles_cxl; } @@ -1073,6 +1083,10 @@ static void cxl_enable_internal_errors(struct pci_dev *dev) static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } +static bool handles_cxl_errors(struct pci_dev *dev) +{ + return false; +} #endif /** @@ -1110,8 +1124,11 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { - cxl_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (handles_cxl_errors(dev)) + cxl_handle_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); }